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US 8,949,106 B2Granted
Just in time compiler in spatially aware emulation of a guest computer instruction set
AssigneeInternational Business Machines Corporation
InventorsTheodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
Life of this patent
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Abstract
A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.
Claims18
A computer program product for emulating execution of a group of Guest instructions of a Guest processor architecture with a single semantic routine of Host instructions of a Host processor architecture, the computer program product comprising non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- monitoring execution of Guest instructions;
- determining that a group of the monitored Guest instructions have been executed, as a group, a predefined number of times;
- responsive to the predefined number of times meeting a threshold value criteria, dynamically selecting the group of Guest instructions, the selected group of Guest instructions beginning with a first Guest instruction and ending with a second Guest instruction;
- Just-In-Time (JIT) compiling the selected group of Guest instructions into a plurality of Host instructions;
- designating a plurality of Host cells in Host memory, each designated Host cell corresponding to a separate respective single Guest cell of Guest memory, each Host cell addressable based on a Guest program counter value, wherein each Guest cell has a size that is equal to a predetermined Guest cell size, each Host cell has a size that is equal to a predetermined Host cell size, and wherein the predetermined Host cell size is greater than the predetermined Guest cell size;
- patching a first Host cell of the plurality of Host cells with Host instructions for executing the plurality of Host instructions, the first Host cell corresponding to a first Guest cell of Guest memory, the first Guest cell corresponding to a beginning portion of said first Guest instruction;
- responsive to the Guest program counter value indicating the first Guest cell corresponding to the first Guest instruction is to be executed, executing the plurality of Host instructions of the patched first Host cell corresponding to the first Guest cell;
- responsive to the Guest program counter value indicating a second Guest cell corresponding to another Guest instruction is to be executed, executing one or more second Host instructions of a second Host cell corresponding to the second Guest cell to emulate execution of the second Guest instruction, the second Guest cell corresponding to a beginning portion of said second Guest instruction;
- wherein each of the plurality of Host cells corresponds to a respective lock bit in a bit significant table, and further comprising:
- before accessing a particular Host cell by the Host processor, determining whether the lock bit corresponding to the particular Host cell in the bit significant table is set to locked;
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to locked, waiting by the Host processor until the lock bit corresponding to the particular Host cell is set to unlocked;
- and
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to unlocked, accessing the particular Host cell by the Host processor.
10 more elements
A computer system for emulating execution of a group of Guest instructions of a Guest processor architecture with a single semantic routine of Host instructions of a Host processor architecture comprising:
- a memory;
- and
- a processor in communication with the memory, the computer system capable of performing a method comprising:
- monitoring execution of Guest instructions;
- determining that a group of the monitored Guest instructions have been executed as a group a predefined number of times;
- responsive to the predefined number of times meeting a threshold value criteria, dynamically selecting the group of Guest instructions, the selected group of Guest instructions beginning with a starting Guest instruction and ending with an ending Guest instruction;
- Just-In-Time (JIT) compiling the selected group of Guest instructions into a plurality of Host instructions;
- designating a plurality of Host cells in Host memory, each designated Host cell corresponding to a separate respective single Guest cell of Guest memory, each Host cell addressable based on a Guest program counter value, wherein each Guest cell has a size that is equal to a predetermined Guest cell size, each Host cell has a size that is equal to a predetermined Host cell size, and wherein the predetermined Host cell size is greater than the predetermined Guest cell size;
- patching a first Host cell of the plurality of Host cells with Host instructions for executing the plurality of Host instructions, the first Host cell corresponding to a first Guest cell of Guest memory, the first Guest cell corresponding to a beginning portion of said starting Guest instruction;
- responsive to the Guest program counter value indicating the first Guest cell corresponding to the starting Guest instruction is to be executed, executing the plurality of Host instructions of the patched first Host cell corresponding to the first Guest cell;
- responsive to the Guest program counter value indicating a second Guest cell corresponding to another Guest instruction is to be executed, executing one or more second Host instructions of a second Host cell corresponding to the second Guest cell to emulate execution of the ending Guest instruction, the second Guest cell corresponding to a beginning portion of said ending Guest instruction;
- wherein each of the plurality of Host cells corresponds to a respective lock bit in a bit significant table, and further comprising:
- before accessing a particular Host cell by the Host processor, determining whether the lock bit corresponding to the particular Host cell in the bit significant table is set to locked;
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to locked, waiting by the Host processor until the lock bit corresponding to the particular Host cell is set to unlocked;
- and
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to unlocked, accessing the particular Host cell by the Host processor.
13 more elements
A computer implemented method for emulating execution of a group of Guest instructions of a Guest processor architecture with a single semantic routine of Host instructions of a Host processor architecture, the method comprising:
- monitoring execution of Guest instructions;
- determining that a group of the monitored Guest instructions have been executed as a group a predefined number of times;
- responsive to the predefined number of times meeting a threshold value criteria, dynamically selecting the group of Guest instructions, the selected group of Guest instructions beginning with a starting Guest instruction and ending with an ending Guest instruction;
- Just-In-Time (JIT) compiling the selected group of Guest instructions into a plurality of Host instructions;
- designating a plurality of Host cells in Host memory, each designated Host cell corresponding to a respective single Guest cell of Guest memory, each Host cell addressable based on a Guest program counter value, wherein each Guest cell has a size that is equal to a predetermined Guest cell size, each Host cell has a size that is equal to a predetermined Host cell size, and wherein the predetermined Host cell size is greater than the predetermined Guest cell size;
- patching a first Host cell of the plurality of Host cells with Host instructions for executing the plurality of Host instructions, the first Host cell corresponding to a first Guest cell of guest memory, the first Guest cell corresponding to a beginning portion of a starting Guest instruction in the series of Guest instructions;
- responsive to the Guest program counter value indicating the first Guest cell corresponding to the beginning portion of the starting Guest instruction is to be executed, executing the plurality of Host instructions of the patched first Host cell corresponding to the first Guest cell;
- responsive to the Guest program counter value indicating a second Guest cell corresponding to a third Guest instruction is to be executed, executing one or more second Host instructions of a second Host cell corresponding to the second Guest cell to emulate execution of an ending Guest instruction in the series of Guest instructions, the second Guest cell corresponding to a beginning portion of the ending Guest instruction;
- wherein each of the plurality of Host cells corresponds to a respective lock bit in a bit significant table, and further comprising:
- before accessing a particular Host cell by the Host processor, determining whether the lock bit corresponding to the particular Host cell in the bit significant table is set to locked;
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to locked, waiting by the Host processor until the lock bit corresponding to the particular Host cell is set to unlocked;
- and
- based on the lock bit corresponding to the particular Host cell in the bit significant table being set to unlocked, accessing the particular Host cell by the Host processor.
10 more elements
Dependencies are inferred from the claim text.