Method and system for power delivery network analysis

A non-transitory computer readable storage medium having a plurality of instructions stored thereon, which, when executed by a processor, cause the processor to perform operations comprising:

• receiving a chip power model, a package power model and a board power model at the computing device;
• providing a user selectable connection interface, wherein the connection interface allows for selection of a board, package and chip connection;
• receiving a selection of at least one of the board, package, and chip connection;
• providing a user selectable pin-mapping file at a graphical user interface, wherein the graphical user interface is configured to display a pin-mapping interface upon selection of the pin-mapping file, the pin-mapping interface allowing for user-selection of a particular component and subsequent display of a plurality of pin names and pin locations for the particular component;
• and
• co-simulating the chip power model, the package power model, and the board power model, wherein co-simulating utilizes, at least in part, a pin-mapping associated with the pin-mapping file.

A computing system for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design comprising:

• at least one processor;
• at least one memory architecture operatively connected with the at least one processor;
• a first software module executed by the at least one processor, wherein the first software module is configured to receive a chip power model, a package power model and a board power model at the computing device;
• a second software module executed by the at least one processor, wherein the second software module is configured to provide a user selectable connection interface, wherein the connection interface allows for selection of a board, package and chip connection;
• a third software module executed by the at least one processor, wherein the third software module is configured to receive a selection of at least one of the board, package, and chip connection;
• a fourth software module executed by the at least one processor, wherein the fourth software module is configured to provide a user selectable pin-mapping file at a graphical user interface, wherein the graphical user interface is configured to display a pin-mapping interface upon selection of the pin-mapping file, the pin-mapping interface allowing for user-selection of a particular component and subsequent display of a plurality of pin names and pin locations for the particular component;
• and
• a fifth software module executed by the at least one processor, wherein the fifth software module is configured to co-simulate the chip power model, the package power model, and the board power model, wherein co-simulating utilizes, at least in part, a pin-mapping associated with the pin-mapping file.