Hardware execution driven application level derating calculation for soft error rate analysis

A computer program product comprising a non-transitory computer readable medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

• implement a unified derating tool, wherein the unified derating tool comprises a machine derating front-end engine used to generate machine derating information for an integrated circuit device design, and an application derating front-end engine used to generate application derating information for the integrated circuit device design;
• execute, by the unified derating tool, the machine derating front-end engine on a simulation of the integrated circuit device design to generate the machine derating information;
• execute, by the unified derating tool, the application derating front-end engine to execute an application workload on existing hardware and inject a fault into the existing hardware during the execution of the application workload cm the existing hardware to generate the application derating information, wherein the application workload is not simulated but actually executed on the existing hardware, wherein the integrated circuit device design comprises new processor chin design, and wherein the existing hardware comprises an existing fabricated processor chip in a same family of processor chips as the new processor chip design;
• and
• combine the machine derating information with the application derating information to generate at least one soft error rate (SER) value for the integrated circuit device design.

An apparatus, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to
• implement a unified derating tool, wherein the unified derating tool comprises a machine derating front-end engine used to generate machine derating information for an integrated circuit device design, and an application derating front-end engine used to generate application derating information for the integrated circuit device design;
• execute, by the unified derating tool, the machine derating front-end engine on a simulation of the integrated circuit device design to generate the machine derating information;
• execute, by the unified derating tool, the application derating front-end engine to execute an application workload on existing hardware and inject a fault into the existing hardware during the execution of the application workload on the existing hardware to generate the application derating information, wherein the application workload is not simulated but actually executed on the existing hardware, wherein the integrated circuit device design comprises a new processor chip design, and wherein the exiting hardware comprises an existing fabricated processor chip in the same family of processor chips as the new processor chip design;
• and
• combine the machine derating information with the application derating information to generate at least one soft error rate (SER) value for the integrated circuit device design.