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US 8,949,083 B2Granted
Modeling gate transconductance in a sub-circuit transistor model
AssigneeGlobalfoundries Inc.
InventorsJia Feng, Zhi-Yuan Wu, Juhi Bansal, Srinath Krishnan
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Abstract
A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.
Claims17
A method for modeling a transistor, comprising:
- providing a transistor model for the transistor having at least a source node, a drain node, a gate node, and a gate transconductance node coupled to the gate node;
- simulating operation of a device including the transistor using the transistor model in a computing apparatus;
- and
- during the simulating, generating an offset voltage at the gate transconductance node depending on a magnitude of a current passing through the transistor, wherein generating the offset voltage further comprises applying an exponential function relating gate transconductance of the transistor to the current.
1 more element
A system, comprising:
- a storage device operable to store a transistor model for a transistor having at least a source node, a drain node, a gate node, and a gate transconductance node coupled to the gate node;
- a computing apparatus operable to execute a simulation application to simulate operation of a device including the transistor using the transistor model and generate an offset voltage at the gate transconductance node depending on a magnitude of a current passing through the device, wherein the simulation application is operable to generate the offset voltage by applying an exponential function relating gate transconductance of the transistor to the current.
A system for modeling a transistor, comprising:
- means for storing a transistor model for the transistor having at least a source node, a drain node, a gate node, and a gate transconductance node coupled to the gate node;
- means for simulating operation of a device including the transistor using the transistor model in a computing apparatus;
- and
- means for generating an offset voltage during the simulating at the gate transconductance node depending on a magnitude of a current passing through the transistor, wherein generating the offset voltage further comprises applying an exponential function relating gate transconductance of the transistor to the current.
1 more element
Dependencies are inferred from the claim text.