Methods of designing integrated circuits and systems thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Tsai Li, Paul Chang, Andy Chang
Life of this patent
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Abstract
A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.
Claims19
A method of designing an integrated circuit, the method comprising:
- performing a pre-layout simulation of the integrated circuit, the pre-layout simulation being performed using a netlist generated from a process design kit (PDK) file, the PDK file including a first plurality of device model cards that are assigned to a first plurality of devices, the first plurality of devices including a first device having a well and at least one first isolation well between the well and a substrate, at least one first parasitic diode being associated with the at least one first isolation well, and the PDK file including information of the at least one first parasitic diode;
- and
- generating a design layout of the integrated circuit corresponding to a result of the pre-layout simulation.
A method of designing an integrated circuit, the method comprising:
- performing a pre-layout simulation of the integrated circuit on a pre-layout simulator, the pre-layout simulation being performed using a netlist generated from a process design kit (PDK) file, the PDK file including a first plurality of device model cards that are assigned to a first plurality of devices, the first plurality of devices including a first device having a well and at least one first isolation well between the well and a substrate, at least one first parasitic diode being associated with the at least one first isolation well, and the PDK file including information of the at least one first parasitic diode;
- generating a design layout of the integrated circuit corresponding to a result of the pre-layout simulation;
- substantially nulling at least one electrical characteristic of the at least one first parasitic diode at a device level;
- extracting at least one electrical characteristic of the at least one first parasitic diode from the design layout;
- and
- performing a post-layout simulation on a post-layout simulator, the post-layout simulation being performed using the extracted at least one electrical characteristic.
A computer system comprising:
- a computer readable storage medium being encoded with a computer program code;
- and
- a processor electrically coupled with the computer readable storage medium, the processor being configured to execute the computer program code for designing an integrated circuit, the computer program code being arranged to cause the processor to:
- perform a pre-layout simulation of the integrated circuit, the pre-layout simulation being performed using a netlist generated from a process design kit (PDK) file, the PDK file including a first plurality of device model cards that are assigned to a first plurality of devices, the first plurality of devices including a first device having a well and at least one first isolation well between the well and a substrate, at least one first parasitic diode being associated with the at least one first isolation well, and the PDK file including information of the at least one first parasitic diode;
- and
- generate a design layout of the integrated circuit corresponding to a result of the pre-layout simulation.
Dependencies are inferred from the claim text.