Shift register and driving method thereof, gate driving apparatus and display apparatus

A shift register, comprising a pulling-up unit, a precharging and resetting unit, a pulling-down unit and an output signal terminal at present stage, wherein:

• the pulling-up unit comprises a first thin film transistor and a pulling-up capacitor connected between a gate and a source of the first thin film transistor in parallel, and the pulling-up unit is connected with the output signal terminal at present stage and is used for pulling up an output signal at present stage so that the output signal at present stage is at a high level;
• the precharging and resetting unit is connected with the gate of the first thin film transistor, an input terminal connected to an output signal of a shift register at previous stage, an input terminal connected to an output signal of a shift register at next stage and a scan control signal input terminal, respectively, and is used for precharging the pulling-up capacitor under controls of a scan control signal and the output signal of the shift register at previous stage before the pulling-up unit pulls up the output signal at present stage so that the first thin film transistor is turned on, and for resetting a potential at the gate of the first thin film transistor under controls of the scan control signal and the output signal of the shift register at next stage after the pulling-up unit pulls up the output signal at present stage so that the output signal at present stage is at a low level;
• the pulling-down unit is connected with the gate of the first thin film transistor and the output signal terminal at present stage, respectively, and is used for pulling down a potential at the gate of the first thin film transistor and the output signal at present stage after the precharging and resetting unit resets the potential at the gate of the first thin film transistor, so that the pulling-up unit is turned off and the output signal at present stage is at the low level;
• the pulling-down unit comprises a dual pulling-down module and a dual pulling-down control module;
• the dual pulling-down module is connected with the dual pulling-down control module, the output signal terminal at present stage and the gate of the first thin film transistor, respectively, and is used for pulling down the output signal at present stage and the potential at the gate of the first thin film transistor alternatively under a control of the dual pulling-down control module;
• wherein the precharging and resetting unit comprises a second thin film transistor and a third thin film transistor;
• the dual pulling-down module comprises a fourth thin film transistor, a fifth thin film transistor and a sixth thin film transistor;
• the dual pulling-down control module comprises an inverter including a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor and a tenth thin film transistor;
• the dual pulling-down control module is connected with a first clock signal input terminal, and the dual pulling-down module is connected with a second clock signal input terminal;
• a gate of the fourth thin film transistor is connected with a gate of the fifth thin film transistor, a drain of the eighth thin film transistor and a source of the tenth thin film transistor, respectively, a source thereof is connected with a power supply VSS, and a drain thereof is connected with the gate of the first thin film transistor, a gate of the seventh thin film transistor, the source of the second thin film transistor and the drain of the third thin film transistor, respectively;
• a source of the fifth thin film transistor is connected with the power supply VSS, and a drain thereof is connected with the output signal terminal at present stage;
• a gate of the sixth thin film transistor is connected with the second clock signal input terminal, and a drain thereof is connected with the output signal terminal at present stage;
• a gate of the seventh thin film transistor is connected with the gate of the first thin film transistor, a source thereof is connected with the power supply VSS, and a drain thereof is connected with a source of the ninth thin film transistor and a gate of the tenth thin film transistor, respectively;
• a gate of the eighth thin film transistor is connected with the gate of the first thin film transistor, a source thereof is connected with the power supply VSS, and a drain thereof is connected with a source of the tenth thin film transistor;
• a gate and a drain of the ninth thin film transistor are connected with the first clock signal input terminal, and a source thereof is connected with a gate of the tenth thin film transistor;
• and
• a drain of the tenth thin film transistor is connected with the first clock signal input terminal.