Clock frequency error detecting device

A clock frequency error detecting device comprising:

• a system storage portion configured to store a synchronization system on the basis of at least one of several types of frame synchronization signals included in a received signal in which one frame is composed of a predetermined number of symbols and a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule;
• a pattern matching portion configured to perform pattern matching between the inputted received signal and the synchronization system stored in the system storage portion;
• a storage portion configured to store an output of the pattern matching portion;
• a correlation calculation portion configured to perform a correlation calculation with the output of the pattern matching portion and an output of the system storage portion;
• a symbol counter configured to count up clocks of a symbol period and to output a count value as a symbol number;
• a timing detection portion configured to detect a frame synchronization signal of each frame on the basis of a correlation result of the correlation calculation portion and to output the symbol number at detection timing;
• and
• a frequency error detection portion configured to detect a change of the symbol number from the timing detection portion and to detect a clock frequency error of the symbol period on the basis of a shift between the detected change and a change of the symbol number based on the predetermined rule,
• wherein the predetermined rule reverses a shift direction for each frame and increases/decreases a shift amount only by a defined amount for each frame, and
• wherein the frequency error detection portion includes:
• a first detection portion configured to detect a change in the symbol number from the timing detection portion for an even-number frame;
• a second detection portion configured to detect a change in the symbol number from the timing detection portion for an odd-number frame, and
• a third detection portion configured to detect a frequency error of a clock of the symbol period by comparing detection results of the first and second detection portions.