Method of static phase offset correction for a linear phase detector
AssigneeAnalog Devices, Inc.
InventorsJohn Kenney, Jeremy Z. Walker
Life of this patent
Estimating the term…
Abstract
A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.
Claims28
A method for calibrating a clock and data recovery circuit, comprising:
- in a first mode of operation, determining phase differences between edges of a sampling clock and a calibration signal, the phase differences represented as positive or negative pulses generated by a phase detector;
- in the first mode of operation, adjusting the phase of the sampling clock to align the sampling clock to the calibration signal;
- in a second mode of operation, determining phase differences between edges of the sampling clock and the calibration signal, the phase differences represented by width of pulses generated by the phase detector;
- in the second mode of operation, adjusting a parameter of the phase detector such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.
A clock and data recovery circuit, comprising:
- a phase detector that includes a bang-bang phase detector and a linear phase detector, the phase detector receives a data signal and a sampling clock and outputs an error signal corresponding to a phase difference between the sampling clock and the data signal;
- a filter for smoothing the error signal output by the phase detector;
- an interpolator that generates the sampling clock by adjusting a reference clock provided to the interpolator based on the filtered error signal;
- and
- a divider for dividing the reference clock and providing the divided reference clock to the phase detector as the data signal during calibration.
A phase detector for a clock and data recovery circuit comprising:
- a linear phase detector including a first set of latches, a second set of latches, and a first set of XOR gates that receive outputs from the first set of latches and the second set of latches, at least one of the XOR gates includes a multiplier for adjusting the output of the linear phase detector during calibration, while the phase of a sampling clock provided to the linear phase detector is kept fixed;
- and
- a bang-bang phase detector that includes the first set of latches, the second set of latches, a third set of latches, and a second set of XOR gates that receive output from the second set of latches and the third set of latches, wherein the outputs of the second set of XOR gates provide pulses indicating a phase difference between a calibration clock and the sampling clock provided to the inputs of the bang phase detector.
A method for calibrating a clock and data recovery circuit, comprising:
- in a first mode of operation, determining phase differences between edges of a sampling clock and a bit pattern, the phase differences represented as positive or negative pulses generated by a phase detector;
- in the first mode of operation, adjusting the phase of the sampling clock to align the sampling clock to the bit pattern;
- in a second mode of operation, determining phase differences between edges of the sampling clock and the bit pattern, the phase differences represented by width of pulses generated by the phase detector;
- and
- in the second mode of operation, adjusting a parameter of the phase detector such that the phase difference between the bit pattern and the sampling clock is a predetermined phase difference value, while keeping the phase of the sampling clock fixed.
Dependencies are inferred from the claim text.