Circuit architecture for I/Q mismatch mitigation in direct conversion receivers

An electrical circuit, comprising:

• a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal;
• an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output;
• a Q-channel mixer configured to inject the second reference signal to the incoming signal to generate a second output;
• a correlation adder configured to add the first output with the second output and generate a third output;
• a first low pass filter configured to attenuate frequencies in the third output to generate a fourth output;
• a first correcting filter configured to filter the fourth output to generate a fifth output;
• a second low pass filter configured to attenuate frequencies in the second output to generate a sixth output;
• and
• a second correcting filter configured to filter the sixth output to generate a seventh output, wherein the first correcting filter and the second correcting filter are configured to reduce a channel impulse response mismatch between the first low pass filter and the second low pass filter.