Reduced state sequence estimation with soft decision outputs

#Certain embodiments of the disclosure relate to communication systems. More specifically, certain embodiments of the disclosure relate to a method and system for improving bit error rate (BER) performance based on a sequence estimation algorithm and forward error correction (FEC).

#Existing communications methods and systems are overly power hungry and/or spectrally inefficient. Complex linear modulation schemes such as, for example, quadrature amplitude modulation (QAM), are used vastly in wireless and non-wireless communications. However, performance of such modulation schemes degrades in the presence of phase noise and non-linear distortion associated with the communication channel. Some of these modulation schemes may perform, for example, 4-5 dB below the Shannon capacity bound in the case of severe phase noise. As higher-order modulation is needed to drive more throughput, the result may be a throughput that is even further away from the Shannon capacity limit. That is, the gap between maximum spectral efficiency and actual spectral efficiency may actually increase with increasing QAM order. In addition, higher-order modulation may also be increasingly sensitive to non-linear distortion.

#Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

#FIG. 1 is a block diagram illustrating an example communication system, in accordance with an embodiment of the disclosure.

#FIG. 2A is a block diagram illustrating an example coupling of an equalizer and a sequence estimation module in a receiver, in accordance with an embodiment of the disclosure.

#FIG. 2B is a block diagram illustrating an example sequence estimation module in a receiver, in accordance with an embodiment of the disclosure.

#As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, a device/module/circuitry/etc. is “operable” to perform a function whenever the device/module/circuitry/etc. comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.

#FIG. 1 is a block diagram illustrating an example communication system, in accordance with an embodiment of the disclosure. Referring to FIG. 1, there is shown a communication system 100. The communication system 100 may comprise a transmitter 120, a communication channel 108 and a receiver 130. The transmitter 120 may comprise, for example, a FEC encoder 101 and a word-to-symbol module 102. The receiver 130 may comprise, for example, a sequence estimation module 112, a symbol-to-word module 114 and a FEC decoder 116. A total partial response filtering function may be split between the transmitter 120 and the receiver 130. In this regard, the transmitter 120 may comprise a pulse shaper 104 and the receiver 130 may comprise an input filter 105. The total partial response filtering function may be split between the pulse shaper 104 and the input filter 105. In an example embodiment of the disclosure, other components such as, for example, an interleaver in the transmitter 120, a timing recovery module in the receiver 130, and/or a de-interleaver in the receiver 130 may also be optionally included without departing from the spirit and scope of various embodiments of the disclosure.

#The FEC encoder 101 may comprise suitable logic, circuitry, interfaces and/or code that may be operable to generate codewords from the input data bitstream. Each codeword may comprise one or more information subwords and one or more parity subwords to enable error correction in the receiver 130. Each subword may be a bit or may be a symbol. The FEC codewords may be generated, for example, in accordance with a Reed-Solomon (RS) code. Forward error correction (FEC) may be used to fix communication errors caused by a communication channel such as the channel 108. Using a good and suitable FEC may improve spectral efficiency of the system 100 and enable it to perform close to the Shannon capacity bound. However, using FEC may introduce overhead, the amount of which depends on the FEC code rate.