Symbol timing recovery with multi-core processor

#1. Field

#Exemplary embodiments of the present invention relate to symbol timing recovery and, in particular, to symbol timing recovery with a multi-core processor.

#2. Description of the Related Art

#The forgoing and other features and advantages of exemplary embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1 illustrates a block diagram of a symbol timing recovery system according to an embodiment of the invention;

#FIG. 2 illustrates a process of dividing a sampled data stream into blocks and sub-blocks for processing according to an embodiment of the invention; and

#Symbol timing recovery of a received signal controls a sample rate at which samples are taken of the received signal, and the symbol timing recovery is used to synchronize a transmitter and receiver using the transmitted signal. Embodiments of the invention utilize a multi-core processor, such as a graphics processing unit (GPU), to accelerate symbol timing recovery by performing timing error detection and symbol timing recovery calculations in parallel by processing cores or threads of the multi-core processor.

#FIG. 1 illustrates a block diagram of symbol timing recovery system 100 according to an embodiment of the invention. In one embodiment, the block diagram of FIG. 1 illustrates a configuration of circuitry in a multi-core processor, such as a graphics processing unit including multiple processing cores. In addition, the block diagram of FIG. 1 may represent the programming of the multi-core processor by software to control the multi-core processor to receive data, process the data, and output the data. In one embodiment, the symbol timing recovery system 100 is a receiver that receives a signal, such as a waveform.

#In FIG. 1, the symbol timing recovery system 100 receives a signal or data stream x[n] having a sampling rate of at least 2 samples per symbol (spS). In other words, each symbol, or bit, of data-to-be-transmitted is sampled twice and then transmitted to the symbol timing recovery system 100, such that each symbol is represented by two bits of transmitted data in the data stream x[n]. In embodiments of the invention, the signal x[n] may be received by wire or wirelessly through the air via an antenna. While a sampling rate of 2 spS is provided in FIG. 1 for the data stream x[n], embodiments of the invention are not limited to this sampling rate.