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US 8,948,215 B2Granted
High speed and high jitter tolerance dispatcher
AssigneeSTMicroelectronics S.r.l.
InventorsMounir Zid, Alberto Scandurra, Carmelo Pistritto, Rached Tourki
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Abstract
A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.
Claims22
A circuit, comprising:
- demultiplexer circuitry configured to receive data from an input and output a plurality of divided data signals, and
- multiplexer circuitry configured to receive a first logic high level at a first input of said multiplexer circuitry, and receive a second logic low level at a second input of said multiplexer circuitry and receive one of said divided data signals at a control input of said multiplexer circuitry,
- wherein said multiplexer circuitry is operable to select between the first logic level at the first input and the second logic level at the second input for output from the multiplexer in response to the received divided data signal, and
- wherein said multiplexer circuitry comprises a plurality of multiplexers, said divided data signals comprises a plurality of data streams, and a respective one of said plurality of data streams is provided to a respective control input of a respective one of said plurality of multiplexers.
1 more element
A circuit, comprising:
- a first demultiplexer having an input configured to receive a serialized data stream and a first and second output configured to produce a first and second divided data stream;
- a second demultiplexer having an input configured to receive the first divided data stream and a first and second output configured to produce a third and fourth divided data stream;
- a third demultiplexer having an input configured to receive the second divided data stream and a first and second output configured to produce a fifth and sixth divided data stream;
- a first multiplexer having a control terminal configured to receive the third divided data stream and a output configured to produce a first parallel data bit;
- a second multiplexer having a control terminal configured to receive the fourth divided data stream and a output configured to produce a second parallel data bit;
- a third multiplexer having a control terminal configured to receive the fifth divided data stream and a output configured to produce a third parallel data bit;
- and
- a fourth multiplexer having a control terminal configured to receive the sixth divided data stream and an output configured to produce a fourth parallel data bit.
5 more elements
A circuit, comprising:
- demultiplexer circuitry having an input configured to receive a serialized data stream including a plurality of channels and further having a plurality of outputs equal in number to said plurality of channels, each output configured to produce a divided data signal, and
- a plurality of multiplexers equal in number to said plurality of channels, each multiplexer having a first input configured to receive a first logic high level signal, a second input configured to receive a second logic low level signal, and a control input configured to receive one of said divided data signals, a plurality of outputs from said plurality of multiplexers configured to output data from said received serialized data stream in a parallel form,
- wherein each multiplexer is operable to select between the first logic level signal at the first input and the second logic level signal at the second input for output from the multiplexer in response to the received divided data signal.
Dependencies are inferred from the claim text.