Dynamic address grouping for parallel programming in non-volatile memory

A non-volatile memory system, comprising:

• a non-volatile memory array;
• a set of data latches;
• and
• one or more control circuits in communication with the plurality of non-volatile storage elements and the set of data latches, the one or more control circuits configured to identify a set of address cycles for writing user data in response to a write request and generate bitmap for the set of address cycles based on the user data to be programmed for individual address cycles of the set, wherein the bitmap data associates two or more address cycles of the set having a number of programmable bits within an allowable threshold, the one or more control circuits configured to store the bitmap data for the set of address cycles and program the user data to be written during the two or more address cycles of the set in one address cycle based on the bitmap data.

A method of programming non-volatile storage, comprising:

• receiving a request to write a set of user data;
• identifying a set of sense amplifier addresses corresponding to a column address for writing the set of user data;
• comparing a number of bits of the user data to be programmed for the column address with an allowable number of parallel programmable bits;
• and
• grouping at least two sense amplifier addresses of the set of sense amplifier addresses into a first group based on a total number of bits to be programmed for the at least two sense amplifier addresses being less than the allowable number of programmable bits.