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US 8,947,970 B2Granted
Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage
AssigneeFreescale Semiconductor, Inc.
InventorsPerry H. Pelley, James D. Burnett
Life of this patent
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Abstract
A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).
Claims19
A memory device, comprising:
- a plurality of static random access memory (SRAM) bit cells;
- a word line driver coupled to provide a word line signal to the bit cells, wherein
- the word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN);
- and
- a block select driver coupled to the word line driver, wherein the block select driver includes a second latch circuit configured to receive a word line clock bar signal through a third pass transistor, and output a block select bar signal that varies between the VDD and the VN.
2 more elements
A static random access memory (SRAM) device, comprising:
- a word line driver coupled to a plurality of SRAM bit cells, wherein the word line driver is configured to:
- receive a global word line signal that is driven between a positive supply voltage and ground,
- receive a word line clock bar signal that is driven between a positive supply voltage (VDD) and a ground voltage at one stage of operation and is tristated at another stage of operation, and
- output a word line signal that varies from the VDD to a negative voltage that is less than the ground voltage.
1 more element
A method for operating a static random access memory (SRAM) memory device, comprising:
- asserting a block select signal in a block select driver;
- asserting a global word line signal in a word line driver when the block select signal is asserted;
- asserting a word line clock bar signal in the block select driver after the block select signal and global word line signals are asserted, the global word line signal being driven between only a positive supply voltage signal (VDD) and ground, and the word line clock bar signal being driven between the VDD and the ground during one stage of operation and being tristated during another stage of operation;
- and
- outputting a word line signal to a bit cell, the word line signal varies between the VDD and a negative voltage signal below ground.
2 more elements
Dependencies are inferred from the claim text.