Memory having power saving mode

A memory having a plurality of modes of operation including a normal mode and a power saving mode, the memory comprising;

• storage circuitry configured to store a data value;
• a pair of bitlines for accessing the data value stored by the storage circuitry;
• bitline precharge circuitry configured, during the normal mode, to selectively couple the bitlines to a precharge node to charge the bitlines to a voltage level of the precharge node and, during the power saving mode, to isolate the bitlines from the precharge node;
• voltage control circuitry configured to control the voltage level of the precharge node;
• wherein during the normal mode, the voltage control circuitry is configured to maintain the precharge node at a first voltage level and, during the power saving mode, the voltage control circuitry is configured to maintain the precharge node at a second voltage level less than the first voltage level, wherein the voltage control circuitry is coupled between the precharge node and a first node for supplying the first voltage level;
• and
• a power down transistor coupled between the first node and a voltage supply input for receiving the first voltage level, wherein in the normal mode and the power saving mode, the power down transistor is in a conductive state and the memory has a power down mode in which the power down transistor is in a less conductive state to isolate the first node from the voltage supply node.

A memory having a plurality of modes of operation including a normal mode and a power saving mode, the memory comprising:

• storage means for storing a data value;
• a pair of bitline means for accessing the data value stored by the storage means;
• bitline precharge means configured, during the normal mode, to selectively couple the bitline means to a precharge node means for charging the bitline means to a voltage level of the precharge node means and, during the power saving mode, to isolate the bitline means from the precharge node means;
• voltage control means for controlling the voltage level of the precharge node means, wherein during the normal mode, the voltage control means is configured to maintain the precharge node means at a first voltage level and during the power saving mode, the voltage control means is configured to maintain the precharge node means at a second voltage level less than the first voltage level, wherein the voltage control means is coupled between the precharge node and a first node for supplying the first voltage level;
• and
• power down transistor means, coupled between the first node and a voltage supply input, for receiving the first voltage level, wherein in the normal mode and the power saving mode, the power down transistor means is in a conductive state and in a power down mode, the power down transistor means is in a less conductive state as compared to said conductive state to isolate the first node from the voltage supply node.

A method of operating a memory having a plurality of modes of operation including a normal mode and a power saving mode, the memory comprising storage circuitry configured to store a data value and a pair of bitlines for accessing the data value stored by the storage circuitry;

• the method comprising:
• during the normal mode, maintaining a precharge node at a first voltage level, and selectively coupling the bitlines to the precharge node to charge the bitlines to the first voltage level of the precharge node;
• and
• during the power saving mode, isolating the bitlines from the precharge node, and maintaining the precharge node at a second voltage level less than the first voltage level, wherein the voltage control circuitry is coupled between the precharge node and a first node for supplying the first voltage level;
• and
• receiving the first voltage level at a power down transistor between the first node and a voltage supply input, wherein in the normal mode and the power saving mode, the power down transistor is in a conductive state and in a power down mode, the power down transistor is in a less conductive state as compared to said conductive state to thereby isolate the first node from the voltage supply node.