Shared integrated sleep mode regulator for SRAM memory
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael Dreesen, Stephen Greenwood, Bruce Doyle
Life of this patent
Estimating the term…
Abstract
Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.
Claims20
A method for regulating sleep mode of a plurality of sub-banks in an SRAM array, comprising:
- isolating, during an access to at least one sub-bank of the plurality of sub-banks that causes the accessed sub-bank to go to an operating voltage, all of the sub-banks from a regulator and isolating the accessed sub-bank from the non-accessed sub-banks while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator;
- comparing a voltage on all sub-banks to a voltage output of the regulator;
- and
- providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non-accessed sub-banks is less than the sleep voltage.
A method of transitioning an accessed SRAM sub-bank to a sleep voltage level after an access operation performed on the accessed SRAM sub-bank at an operating voltage level comprising:
- opening a feedback loop maintained by a regulator providing the sleep voltage to an SRAM array containing the accessed SRAM sub-bank and a plurality of additional SRAM sub-banks;
- opening the feedback loop upon execution of the access operation to allow the accessed SRAM sub-bank to go to the operating voltage level;
- isolating the accessed SRAM sub-bank from the additional SRAM sub-banks upon execution of the access operation;
- and
- closing the feedback loop upon completion of the access operation to allow the accessed SRAM sub-bank to return to the sleep voltage level.
A circuit comprising:
- a regulator configured to provide a bias voltage to an input stage of a load memory array and each of the sub-banks of the plurality of sub-banks through a regulator that is coupled to the SRAM array through a feedback loop upon an access to at least one accessed sub-bank of the plurality of sub-banks that causes the accessed sub-bank to go to an operating voltage;
- an isolator configured to isolate the accessed sub-bank from the non-accessed sub-banks of the plurality of sub-banks during the access to the accessed sub-bank;
- a comparator configured to compare a voltage on all sub-banks to a voltage output of the regulator;
- and
- a switch configured to close the feedback loop to provide a sleep voltage level to all of the sub-banks through the regulator.
Dependencies are inferred from the claim text.