Power gated memory device with power state indication
AssigneeLSI Corporation
InventorsSathappan Palaniappan, Romeshkumar Mehta, Dharmesh Tirthdasani
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Abstract
A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
Claims19
A memory device comprising:
- a plurality of power gates, each of the power gates being configured to independently control a power down of corresponding circuitry in the memory device;
- and
- state signaling circuitry, the state signaling circuitry operative to produce a power state output signal indicative of when the power gates are configured such that the memory device is fully powered up.
A method for performing power gating in a memory device, the method comprising the steps of:
- forming a plurality of power gates into the memory device, each of the power gates being configured to independently control a power down of corresponding circuitry in the memory device;
- and
- forming state signaling circuitry into the memory device, the state signaling circuitry operative to produce a power state output signal indicative of when the power gates are configured such that the memory device is fully powered up.
An integrated circuit comprising a memory device, the memory device comprising:
- a plurality of power gates, each of the power gates being configured to independently control a power down of corresponding circuitry in the memory device;
- and
- state signaling circuitry, the state signaling circuitry operative to produce a power state output signal indicative of when the power gates are configured such that the memory device is fully powered up.
Dependencies are inferred from the claim text.