Variable pre-charge levels for improved cell stability
AssigneeApple Inc.
InventorEdward M McCombs
Life of this patent
Estimating the term…
Abstract
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal.
Claims19
A memory, comprising:
- a plurality of data lines, wherein each data line of the plurality of data lines is coupled to a plurality of data storage cells;
- and
- a plurality of pre-charge circuits, wherein each pre-charge circuit of the plurality of pre-charge circuits is coupled to a respective data line of the plurality of data lines, and wherein each pre-charge circuit of the plurality of pre-charge circuits is configured to:
- charge the respective data line of the plurality of data lines to a first voltage level responsive to a first control signal, wherein the first control signal is asserted in response to receiving a command to access the memory;
- and
- charge the respective data line of the plurality of data lines to a second voltage level responsive to an assertion of a respective one of a plurality of second control signals in response to a determination that the command specifies a read operation wherein the first voltage level is different from the second voltage level.
A method, comprising:
- receiving a command and an address;
- charging each data line of a plurality of data lines to a first voltage level responsive to receiving the command, wherein each data line is coupled to a plurality of data storage cells;
- detecting a read operation dependent upon the received command;
- decoding the received address;
- selecting a given data line of the plurality of data lines dependent upon the decoded received address;
- and
- charging, responsive to the detection of the read operation, the given data line of the plurality of data lines to a second voltage level wherein the first voltage level is different from the second voltage level.
A system, comprising:
- a processor;
- and
- one or more memories, wherein each memory of the one or more memories comprises:
- a control circuit configured to:
- generate a pre-charge signal responsive to the detection of a start of a memory access;
- and
- detect when the memory access is a read operation dependent upon a received command;
- a decode circuit configured to, responsive to the detection of the read operation, activate one of a plurality of pre-charge selection signals dependent upon a received address;
- and
- a plurality of columns coupled to the respective plurality of pre-charge selection signals, wherein each column of the plurality of columns comprises:
- a data line, wherein the data line is coupled to a plurality of data storage cells;
- and
- a pre-charge circuit coupled to the data line, wherein the pre-charge circuit is configured to:
- charge the data line to a first voltage level responsive to the pre-charge signal;
- and
- charge the data line to a second voltage level responsive to the activation of a respective one of the plurality pre-charge selection signals wherein the first voltage level is different from the second voltage level.
Dependencies are inferred from the claim text.