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US 8,947,962 B2Granted
On-die termination of address and command signals
AssigneeRambus Inc.
InventorsIan Shaeffer, Kyung Suk Oh
Life of this patent
Estimating the term…
Abstract
A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.
Claims20
A memory controller configured to be connected to one or more memory devices via an address and control (RQ) bus, wherein:
- each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the address and control (RQ) bus;
- and
- the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices by driving control signals on a plurality of ODT control lines.
Dependencies are inferred from the claim text.