Latent slow bit detection for non-volatile memory

A method for detecting a latent slow bit in a non-volatile memory (NVM) comprising:

• altering a storage state of the plurality of bits of the NVM;
• determining a last changed bit threshold voltage level of a last changed bit of the plurality of bits, wherein the last changed bit of the plurality of bits is a bits whose storage state is changed last by the altering the storage state of the plurality of bits;
• performing a state change verification of the bits using an adjusted state change verification voltage level, the adjusted state change verification voltage level imposing a more stringent threshold voltage for verifying an altered storage state of a bit of the plurality of bits than the last changed bit threshold voltage level;
• comparing a number of failing bits which failed the state change verification to a failing bits threshold;
• and
• rejecting a device comprising the NVM in response to the number of failing bits being fewer than the failing bits threshold.

A non-volatile memory (NVM) comprising:

• a bitcell array comprising a plurality of bitcells for storing a plurality of bits;
• a charge pump coupled to the plurality of bitcells;
• and
• an NVM controller coupled to the bitcell array and to the charge pump, the NVM controller comprising control logic to control the charge pump to provide a normal bias voltage for altering the plurality of bits, to control the charge pump to provide at least one reduced bias voltage for altering the plurality of bits, wherein the at least one reduced bias voltage is less potent than the normal bias voltage, to determine a last changed bit threshold voltage level of a last changed bit of the plurality of bits, to control the charge pump to provide an adjusted state change verification voltage level, the adjusted state change verification voltage level selected from a group consisting of an erase verify voltage level, the erase verify voltage level being lower than a least erased bit threshold voltage level, and a program verify voltage level, the program verify voltage level being higher than a least programmed bit threshold voltage level, to perform a state change verification of the bits using the adjusted state change verification voltage level, to compare a number of failing bits which failed the state change verification to a failing bits threshold, and, when the number of failing bits is fewer than the failing bits threshold, to reject the NVM as defective.