Delay circuit and latency control circuit of memory, and signal delay method thereof
AssigneeHynix Semiconductor Inc.
InventorJeong-Tae Hwang
Life of this patent
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Abstract
A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.
Claims18
A delay circuit, comprising:
- a delay unit configured to generate a delayed transfer signal by delaying a transfer signal wherein the transfer signal is enabled when a first signal or a second signal is applied;
- a distinguishment signal generation unit configured to generate a distinguishment signal which has a first value when the transfer signal is enabled in response to the applied first signal, and has a second value when the transfer signal is enabled in response to the applied second signal;
- and
- a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal when the distinguishment signal has the first value, or output the delayed transfer signal as a second delayed signal when the distinguishment signal has the second value.
A latency control circuit of a memory device, comprising:
- a command signal delay unit configured to generate a delayed command signal by delaying a command signal, wherein the command signal is enabled when a read command or a write command is applied, by a latency;
- a distinguishment signal generation unit configured to generate a distinguishment signal which has a first value when the command signal is enabled in response to the applied read command, and has a second value when the command signal is enabled in response to the applied write command;
- and
- a delayed command generation unit configured to output the delayed command signal as a delayed read command when the distinguishment signal has the first value, or output the delayed command signal a delayed write command when the distinguishment signal has the second value.
A method for delaying a signal, comprising:
- generating a transfer signal which is enabled when a first signal or a second signal is applied;
- generating a distinguishment signal which has a first value when the transfer signal is enabled in response to the applied first signal, and has a second value when the transfer signal is enabled in response to the applied second signal;
- generating a delayed transfer signal by delaying the transfer signal;
- and
- outputting the delayed transfer signal as a first delayed signal when the distinguishment signal has the first value, and output the delayed transfer signal as a second delayed signal when the distinguishment signal has the second value.
Dependencies are inferred from the claim text.