Semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Yeop Baeck, Jin-Sung Kim, Jang-Hwan Yoon
Life of this patent
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Abstract
A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.
Claims18
A semiconductor memory device comprising:
- at least one memory cell connected to an internal voltage line that receives a cell power supply voltage;
- a write assist circuit connected to the internal voltage line, the write assist circuit configured to lower a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and configured to maintain the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal, the second period succeeding the first period;
- and
- a precharge circuit connected between a power supply voltage and the internal voltage line, the precharge circuit configured to precharge the internal voltage line.
A semiconductor memory device comprising:
- at least one memory cell connected to an internal voltage line that receives a cell power supply voltage;
- and
- a write assist circuit connected to the internal voltage line, the write assist circuit configured to lower a level of the cell power supply voltage to a target level during a first period of a write operation to the memory cell and configured to maintain the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal and a delay control signal,
- wherein the write assist circuit comprises:
- a first pull-down unit configured to be turned on during the first and second periods in response to the write assist control signal to provide a first pull-down path from the internal voltage line to a ground voltage;
- and
- a second pull-down unit configured to be turned on during the first period and configured to be turned off during the second period in response to the delay control signal to provide a second pull-down path from the internal voltage line to the ground voltage.
A memory card, comprising:
- a nonvolatile memory device;
- a semiconductor memory device, comprising:
- at least one memory cell connected to an internal voltage line that receives a cell power supply voltage, and
- a write assist circuit connected to the internal voltage line, the write assist circuit configured to lower a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell by enabling a first pull-down path from the internal voltage line and a second pull-down path from the internal voltage line and configured to maintain the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal by enabling the first pull-down path and disabling the second pull-down path;
- and
- a controller configured to receive data and control the nonvolatile memory device to store the received data, and configured to control the semiconductor memory device as a buffer to temporarily store the data to be stored in the nonvolatile memory device.
Dependencies are inferred from the claim text.