Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsKyo-Suk Chae, Satoru Yamada
Life of this patent
Estimating the term…
Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsKyo-Suk Chae, Satoru Yamada
Estimating the term…
A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.
A semiconductor memory device comprising:
A semiconductor memory device comprising:
A memory device comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
This application claims the benefit of Korean Patent Application No. 10-2012-0042177, filed on Apr. 23, 2012, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
Various example embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a column select transistor with improved operation characteristics.
A dynamic random access memory (DRAM), which is an example of semiconductor memory devices, charges data signals to a capacitor of a memory cell during a writing operation and outputs data signals stored in a capacitor of a memory cell during a reading operation. The DRAM includes an array of a plurality of memory cells, where the writing operation and the reading operation with respect to the plurality of memory cells may be performed by controlling word lines each of which is connected to memory cells arranged on a same row and bit lines each of which is connected to memory cells arranged on a same column. Operation characteristics of the reading operation and the writing operation may be affected by an operation of the column select transistor.
Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic circuit diagram of a semiconductor memory device according to one embodiment;
FIG. 2 is a schematic circuit diagram of a semiconductor memory device according to one embodiment;
Example embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown.
The present disclosure may, however, be embodied in many alternate forms and should not be construed as being limited to the embodiments set forth herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms, such as “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
From the US filing history. Foreign family members aren’t listed.
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
Arrangements for writing information into, or reading information out from, a digital
Read-write [R-W] circuits: bit-line management or control circuits
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
About 6 years 6 months of term left · ends 13 Apr 2033 (estimated)