Mode changing circuitry
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBing Wang, Kuoyuan (Peter) Hsu
Life of this patent
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Abstract
A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
Claims20
A circuit comprising:
- a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate;
- a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate;
- a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate;
- and
- a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate;
- wherein
- the first PMOS gate serves as an input and is configured to receive an input voltage having a voltage level determined based on an operational voltage;
- the first PMOS drain is coupled to the first NMOS drain and the second PMOS gate;
- the first PMOS source is coupled to the operational voltage;
- the first NMOS gate is coupled to the operational voltage;
- the second PMOS drain is coupled to the second NMOS drain, and serves as an output;
- and
- a driving capability of the first NMOS transistor is less than that of the first PMOS transistor.
A circuit comprising:
- a memory cell having a ground reference node;
- a switch coupled to the ground reference node;
- and
- a mode changing circuit having an output coupled to the switch and configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at a first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
A method comprising:
- driving a control signal to a gate of a transistor coupled to a node;
- a conduction state of the transistor causing a change between a first state of the node and a second state of the node;
- and
- switching between the first state and the second state by a circuit based on a voltage change at an input of the circuit in response to a change in an operational voltage and/or temperature that causes a change to the control signal.
Dependencies are inferred from the claim text.