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US 8,947,947 B2Granted
Integrated circuit and memory device
AssigneeSK hynix Inc.
InventorsJeongsu Jeong, Jeongtae Hwang, Igsoo Kwon, Yeonuk Kim
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.
Claims10
An integrated circuit, comprising:
- a plurality of internal circuits;
- an e-fuse array circuit configured to store a data used by the internal circuits;
- and
- a fuse circuit configured to store a trimming data to set the e-fuse array circuit,
- wherein a capacity of the trimming data stored in the fuse circuit is less than 1/100 of a capacity of a data stored in the e-fuse array circuit.
2 more elements
A memory device, comprising:
- a plurality of memory banks;
- a plurality of repair circuits configured to perform a repair operation of the memory banks;
- a plurality of test mode circuits configured to perform a setup operation of the memory device;
- an e-fuse array circuit configured to store a repair data to be used by the repair circuits and a setup data to be used by the test mode circuits;
- and
- a fuse circuit configured to store a trimming data to set the e-fuse array circuit.
3 more elements
An integrated circuit, comprising:
- a plurality of internal circuits;
- an e-fuse array circuit configured to store a data used by the internal circuit;
- and
- a fuse circuit configured to store a trimming data to set the e-fuse array circuit,
- wherein the e-fuse array circuit comprises:
- a plurality of memory cells each including an c-fuse and a switch;
- a voltage providing circuit configured to supply a voltage having a level determined in response to the trimming data;
- a row control circuit configured to transfer the voltage supplied from the voltage providing circuit to a memory cell selected from the memory cells;
- and
- a column control circuit configured to sense a data of the selected memory cell using a reference voltage generated in response to the trimming data, and
- wherein a capacity of the trimming data stored in the fuse circuit is less than 1/100 of a capacity of a data stored in the c-fuse array circuit.
8 more elements
Dependencies are inferred from the claim text.