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US 8,947,942 B2Granted
Semiconductor memory chip and multi-chip package using the same
AssigneeSK hynix Inc.
InventorsBok Rim Ko, Kwang Soon Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a swap mode.
Claims15
A semiconductor memory chip comprising:
- a first pad unit configured to receive a first data and a first strobe signal;
- a second pad unit configured to receive a second data and a second strobe signal;
- a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a second mode;
- and
- a second selection transfer unit configured to transfer the second data and the second strobe signal to the second write path circuit in the first mode and a third mode.
2 more elements
A semiconductor memory chip comprising:
- a first multiplexer configured to multiplex data from a memory core and output the multiplexed data to a first pad unit through a first read path circuit in a first mode and a second mode;
- a first selection transfer unit configured to transfer a first data and a first strobe signal, which are inputted through the first pad unit, to a first write path circuit in the first mode, and transfer the first data and the first strobe signal to a second write path circuit in the second mode;
- and
- a second selection transfer unit configured to transfer a second data and a second strobe signal, which are inputted through a second pad unit, to the second write path circuit in the first mode and a third modes.
1 more element
A multi-chip package configured to receive a first, second, third, and fourth data and a first, second, third, and fourth strobe signals, comprising:
- a first semiconductor memory chip comprising:
- a first selection transfer unit configured to transfer the first data and the first strobe signal, which are inputted through a first pad unit, to a first write path circuit in a first mode, and transfer the first data signal and the first strobe signal to a second write path circuit in a second mode;
- and
- a second selection transfer unit configured to transfer the second data and the second strobe signal, which are inputted through a second pad unit, to the second write path circuit in the first mode and a third mode;
- a second semiconductor memory chip comprising:
- a first selection transfer unit configured to transfer the third data and the third strobe signal, which are inputted through a first pad unit, to a first write path circuit in the first mode, and transfer the third data and the third strobe signal to a second write path circuit in the second mode;
- and
- a second selection transfer unit configured to transfer the fourth data and the fourth strobe signal, which are inputted through a second pad unit, to the second write path circuit in the first and third modes;
- and
- a package pad unit coupled to the first and second pad units of the first semiconductor memory chip and to the first and second pad units of the second semiconductor memory chip.
7 more elements
Dependencies are inferred from the claim text.