Structure and method for healing tunnel dielectric of non-volatile memory cells
AssigneeFreescale Semiconductor, Inc.
InventorsFuchen Mu, Yanzhuo Wang
Life of this patent
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Abstract
A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.
Claims20
A semiconductor device comprising:
- an array of memory cells, wherein each of the memory cells includes a tunnel dielectric, a well region including a first current electrode, a second current electrode, and a channel region between the first current electrode and the second current electrode, a floating gate wherein the tunnel dielectric is over the channel region and the floating gate is over the tunnel dielectric, an interface dielectric over the floating gate, and a control gate over the interface dielectric;
- and
- a controller coupled to the memory cells, wherein the controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric, wherein the first voltage is sufficient to draw at least some of the trapped electrons out of the tunnel dielectric.
A method comprising:
- performing a healing process to reduce trapped holes and electrons in a tunnel dielectric of a semiconductor memory cell, wherein the tunnel dielectric is located between first and second current electrodes and a floating gate, and when performing the healing process, applying a healing voltage to the first electrode of the memory cell, wherein the healing voltage is sufficient to draw at least some of the trapped electrons out of the tunnel dielectric while being low enough to avoid moving electrons from the floating gate to the tunnel dielectric.
A semiconductor device comprising:
- an array of nonvolatile memory cells;
- and
- a controller coupled to the array, wherein the controller is configured with logic operable to perform a healing process to reduce trapped holes and electrons in a tunnel dielectric, wherein the tunnel dielectric is located over a well region with current electrodes and a floating gate in the memory cells, and the healing process includes applying a first voltage to one of the current electrodes and a second voltage to a control gate and another one of the current electrodes, and wherein the first voltage is sufficient to draw at least some of the trapped electrons out of the tunnel dielectric.
Dependencies are inferred from the claim text.