Low voltage programming in NAND flash

A memory comprising:

• a plurality of memory cells arranged in series in a semiconductor body;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
• biasing one of first and second ends of the plurality of memory cells to a drain side voltage, and another of the first and second ends to a source side voltage during a program interval,
• applying drain-side pass voltages to word lines between the selected word line and said one of first and second ends during the program interval,
• applying source-side pass voltages to word lines between the selected word line and said other of first and second ends during a program interval, and
• iteratively applying a program voltage to the selected word line during the program interval, and a switching voltage pulse to a word line and corresponding memory cell adjacent the selected word line and selected memory cell to control conductance during the program interval, followed by a verify and retry if the verify fails, wherein in each iteration the switching voltage pulse increases or decreases in magnitude, and in at least one iteration during the program interval the switching voltage pulse is a negative voltage;
• a first switch between a reference line and the first end of the plurality of memory cells and a second switch between a first bit line and the second end of the plurality of memory cells;
• and
• an additional dummy cell not used for data storage, in series with the plurality of memory cells in the semiconductor body and an additional dummy word line, and disposed between the plurality of memory cells and one of the first switch and the second switch, and wherein the control circuitry applies the switching voltage to the additional dummy word line during the program interval for a target cell adjacent the additional dummy word line.

A memory comprising:

• a plurality of bit lines and a plurality of common source lines;
• a plurality of memory cells;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells, wherein the plurality of memory cells is arranged as a first NAND string coupled to a first bit line in the plurality of bit lines and a first common source line in the plurality of common source lines;
• a plurality of additional NAND strings coupled to the plurality of word lines, the plurality of bit lines, and the plurality of common source lines, wherein a second NAND string in the plurality of additional NAND strings is coupled to word lines in the plurality of word lines shared with the first NAND string, to the first bit line and to a second common source line in the plurality of common source lines;
• and
• control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the first NAND string corresponding to a selected word line by:
• biasing one of first and second ends of the first NAND string to a drain side voltage via the first common source line, and another of the first and second ends to a source side voltage via the first bit line during a program interval,
• applying drain-side pass voltages to word lines between the selected word line and said one of first and second ends during the program interval,
• applying source-side pass voltages to word lines between the selected word line and said other of first and second ends during a program interval, and
• iteratively applying a program voltage to the selected word line during the program interval, and a switching voltage pulse to a word line and corresponding memory cell adjacent the selected word line and selected memory cell to control conductance during the program interval, followed by a verify and retry if the verify fails, wherein in each iteration the switching voltage pulse increases or decreases in magnitude, and in at least one iteration during the program interval the switching voltage pulse is a negative voltage.

A memory comprising:

• a plurality of memory cells arranged in series in a semiconductor body;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
• biasing one of first and second ends of the plurality of memory cells to a drain side voltage, and another of the first and second ends to a source side voltage during a program interval,
• applying drain-side pass voltages to word lines between the selected word line and said one of first and second ends during the program interval,
• applying source-side pass voltages to word lines between the selected word line and said other of first and second ends during a program interval, and
• iteratively applying a program voltage to the selected word line during the program interval, and a switching voltage pulse to a word line and corresponding memory cell adjacent the selected word line and selected memory cell to control conductance during the program interval, followed by a verify and retry if the verify fails, wherein in each iteration the switching voltage pulse increases or decreases in magnitude within a range, and in at least one iteration during the program interval the switching voltage pulse is a negative voltage;
• and
• wherein the control circuitry applies switching voltages which change during the program interval from a level that blocks current flow to a level within the range that supports hot carrier injection to more than one word line during the program interval.

A memory comprising:

• a NAND string including a plurality of memory cells arranged in series in a semiconductor body;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• and
• control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
• controlling conductance in the NAND string by applying a switching voltage pulse to a word line adjacent the selected word line to induce an effective source in a first semiconductor body region on one side of a selected cell and to induce an effective drain in a second semiconductor body region on another side of the selected cell in the NAND string;
• biasing the first semiconductor body region to a source side voltage;
• biasing the second semiconductor body region to a drain side voltage;
• and
• iteratively applying a program potential greater than a hot carrier injection barrier level to the selected cell during a program interval, followed by a verify and retry if the verify fails, wherein in each iteration the switching voltage pulse increases or decreases in magnitude, and in at least one iteration during the program interval the switching voltage pulse is a negative voltage.

A method for inducing hot carrier injection in a selected cell in a NAND string in a NAND array, comprising:

• controlling conductance in the NAND string by applying a switching voltage pulse to a word line adjacent the selected word line to induce an effective source on a first side of a selected cell and to induce an effective drain on a second side of the selected cell in the NAND string;
• biasing the effective drain to a drain side voltage;
• biasing the effective source to a source side reference voltage;
• iteratively applying a program potential greater than a hot carrier injection barrier level to the selected cell during a program interval, followed by a verify and retry if the verify fails, wherein in each iteration the switching voltage pulse increases or decreases in magnitude, and in at least one iteration during the program interval the switching voltage pulse is a negative voltage.