Two-transistor non-volatile memory cell and related program and read methods
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTe-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
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Abstract
A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
Claims20
A memory device comprising:
- an N-channel transistor having a drain terminal electrically connected to a word line, and a source terminal electrically connected to a first bit line;
- and
- a P-channel transistor having a source terminal electrically connected to the word line, and a drain terminal electrically connected to a second bit line;
- wherein gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
A method of programming a memory device, the method comprising:
- applying a first voltage to a drain terminal of an N-channel transistor and a source terminal of a P-channel transistor sharing a floating gate with the N-channel transistor;
- and
- applying a second voltage to at least one of a source terminal of the N-channel transistor, a drain terminal of the P-channel transistor, and a well terminal of the P-channel transistor;
- wherein the first voltage is higher than the second voltage by a channel hot injection programming threshold.
A method of reading a memory device, the method comprising:
- applying a read voltage to a drain terminal of an N-channel transistor and a source terminal of a P-channel transistor sharing a floating gate with the N-channel transistor;
- and
- sensing at least one of a first output current at a source terminal of the N-channel transistor and a second output current at a drain terminal of the P-channel transistor.
Dependencies are inferred from the claim text.