Sharing local control lines across multiple planes in a memory device

A memory device comprising:

• a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate;
• and
• a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate;
• wherein the first and second select gates are coupled to a shared local control line and only one global select gate couples the shared local control line to a global control line;
• wherein the first vertical string of memory cells is one of a plurality of first vertical strings of memory cells of the first vertical plane of memory cells and the second vertical string of memory cells is one of a plurality of second vertical strings of memory cells of the second vertical plane of memory cells;
• wherein a plurality of memory cells of the first vertical plane of memory cells are commonly coupled to a same first access line, the plurality of memory cells of the first vertical plane of memory cells commonly coupled to the same first access line comprising a memory cell from each of the plurality of first vertical strings of memory cells of the first vertical plane of memory cells;
• and
• wherein a plurality of memory cells of the second vertical plane of memory cells are commonly coupled to a same second access line, the plurality of memory cells of the second vertical plane of memory cells commonly coupled to the same second single access line comprising a memory cell from each of the plurality of second vertical strings of memory cells of the second vertical plane of memory cells.

A method for accessing a selected memory cell comprising:

• activating a global select gate to couple a global control line to an associated local control line that is shared by a plurality of local select gates across a plurality of planes of memory cells, wherein the selected memory cell is in one of the plurality of planes;
• and
• biasing an access line coupled to a control gate of the selected memory cell;
• wherein the plurality of planes of memory cells comprises a first plane of memory cells that comprises a plurality of memory cells commonly coupled to a first access line and a second plane of memory cells that comprises a plurality of memory cells commonly coupled to a second access line different than the first access line, the first and second access lines commonly coupled to a same local access line.

A system comprising:

• a controller configured to control the memory system;
• and
• a memory device coupled to the controller the memory device comprising:
• a plurality of vertical planes of memory cells, each plane having at least one series string of memory cells, each series string of memory cells having a local select gate wherein a control gate of each corresponding local select gate of the plurality of planes of memory cells is coupled to a local shared control line and only one global select gate is configured to control access for the local shared control line to a global control line;
• wherein the plurality of vertical planes of memory cells comprises a first vertical plane of memory cells that comprises a plurality of memory cells commonly coupled to a first access line and a second vertical plane of memory cells that comprises a plurality of memory cells commonly coupled to a second access line different than the first access line, the first and second access lines commonly coupled to a same local access line;
• and
• wherein the plurality of memory cells commonly coupled to the first access line comprises a memory cell from the at least one series string of memory cells of the first vertical plane of memory cells and the plurality of memory cells commonly coupled to the second access line comprises a memory cell from the at least one series string of memory cells of the second vertical plane of memory cells.

A system comprising:

• a controller configured to control the system;
• and
• a memory device coupled to the controller the memory device comprising:
• a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate;
• and
• a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate;
• wherein the first and second select gates are coupled to a first shared local control line and only a first global select gate couples the first shared local control line to a first global control line;
• wherein the first vertical string of memory cells is one of a plurality of first vertical strings of memory cells of the first vertical plane of memory cells and the second vertical string of memory cells is one of a plurality of second vertical strings of memory cells of the second vertical plane of memory cells;
• wherein a plurality of memory cells of the first vertical plane of memory cells are commonly coupled to a same first access line, the plurality of memory cells of the first vertical plane of memory cells commonly coupled to the same first access line comprising a memory cell from each of the plurality of first vertical strings of memory cells of the first vertical plane of memory cells;
• wherein a plurality of memory cells of the second vertical plane of memory cells are commonly coupled to a same second access line, the plurality of memory cells of the second vertical plane of memory cells commonly coupled to the same second single access line comprising a memory cell from each of the plurality of second vertical strings of memory cells of the second vertical plane of memory cells;
• and
• wherein the first and second same single access lines are commonly coupled to a same local access line.

A memory device comprising:

• a plurality of vertical planes of memory cells, each plane having a plurality of vertical strings of memory cells, each vertical string coupled to a respective local select gate, control gates of each of the corresponding local select gates of each plane coupled to a corresponding local control line wherein each corresponding local control line is coupled to a corresponding global control line only through one corresponding global select gate,
• wherein the plurality of vertical planes of memory cells comprises a first vertical plane of memory m rises a plurality of memo cells commonly coupled to a first access line and a second vertical plane of memory cells that comprises a plurality of memory cells commonly coupled to a second access line different than the first access line, the first and second access lines commonly coupled to a same local access line;
• and
• wherein the plurality of memory cells commonly coupled to the first access line comprises a memory cell from each of plurality of vertical strings of memory cells of the first vertical plane of memory cells and the plurality of memory cells commonly coupled to the second access line comprises a memory cell from each of plurality of vertical strings of memory cells of the second vertical plane of memory cells.