Semiconductor memory device for storing multivalued data

A semiconductor memory device comprising:

• first and second bit lines;
• first, second and third word lines;
• a plurality of memory cells including first, second, third and fourth memory cells, each memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the first memory cell connected to the first word line and coupled to the first bit line, a source of the second memory cell connected to a drain of the first memory cell, the third memory cell being adjacent to the second memory cell along the second word line, connected to the second word line and coupled to the second bit line, the fourth memory cell connected to the third word line and coupled to the first bit line, a source of the fourth memory cell connected to a drain of the second memory cell;
• and
• a write circuit configured to write a first bit of data into the first memory cell, write a second bit of data into the second memory cell, write a third bit of data into the third memory cell and write a fourth bit of data into the fourth memory cell, before writing a fifth bit of data into the second memory cell without erasing the second bit of data in the second memory cell, wherein:
• the write circuit is configured to write the second bit of data into the second memory cell by making a threshold voltage of the second memory cell higher than a first verify potential, according to a first logical state of the second bit of data;
• the write circuit is configured to write the fifth bit of data into the second memory cell by making the threshold voltage of the second memory cell, which has been made higher than the first verify potential, higher than a second verify potential, according to a first logical state of the fifth bit of data;
• the write circuit is configured to write the fifth bit of data into the second memory cell by making the threshold voltage of the second memory cell, which has been made higher than the first verify potential, higher than a third verify potential, according to a second logical state of the fifth bit of data;
• and
• the third verify potential is higher than the second verify potential.