Gated diode memory cells
AssigneeInternational Business Machines Corporation
InventorsWing K. Luk, Robert H. Dennard
Life of this patent
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Abstract
A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
Claims17
A gated diode memory cell, comprising:
- at least one switching unit, including a first field effect transistor (FET) and a second FET;
- and
- a directional unit, including a gated diode, the directional unit being in signal communication with the at least one switching unit,
- wherein a source of the first FET is in signal communication with a gate of the gated diode,
- wherein a gate of the first FET is electrically connected to a write wordline of the gated diode memory cell, and
- wherein the first FET and the second FET comprise respective drain terminals electrically connected to a bitline of the gated diode memory cell,
- wherein the gate of the gated diode forms one terminal of a storage cell of the gated diode memory cell and a source of the gated diode forms another terminal of the storage cell of the gated diode memory cell, and
- wherein none of the switching units of the gated diode memory cell are directly connected to a read wordline of the gated diode memory cell.
Dependencies are inferred from the claim text.