Thyristor memory cell integrated circuit

#1. Field

#The present application relates to integrated circuits. More specifically, the present application relates to memory integrated circuits that store data bit values in an array of memory cells.

#2. State of the Art

#FIG. 1 is a schematic diagram of a thyristor memory cell integrated circuit according to the present application.

#FIG. 2 is a diagram showing the current-voltage characteristics of a resistive load element and thyristor device of the thyristor memory cell of FIG. 1, including such current-voltage characteristics corresponding to volatile “0” and “1” bit values.

#FIG. 3 is a schematic top view of an exemplary thyristor memory cell integrated circuit according to the present application.

#FIG. 1 is a schematic diagram of a thyristor memory cell integrated circuit according to the present application. The thyristor memory cell integrated circuit includes an array of thyristor memory cells integrally formed on a substrate where each thyristor memory cell includes two devices—a thyristor device and a resistive load element. The thyristor device and the resistive load element define a switchable current path through the thyristor device and the resistive load element, where the current path is switched ON when the thyristor device operates in its conducting/ON state and where the current path is switched OFF when the thyristor device operates in its non-conducting/OFF state. The thyristor device includes complementary n-type and p-type modulation doped quantum well (QW) interfaces 11, 13 formed between top P+ layer(s) 15 and bottom N+ layer(s) 17 on a substrate 18. In one embodiment, the thyristor device is defined by a mesa that includes a refractory anode terminal 19 formed above the top P+ layer 15. A cathode terminal 21 is operably coupled to the bottom N+ layer 17. The potential of the cathode terminal 21 is fixed at ground or a negative potential. An n-channel injector terminal 23 and a p-channel injector terminal 25 are electrically coupled to the n-type and p-type modulation doped quantum well interfaces 11, 13, respectively. The resistive load element 27 can be integrally formed above the top anode terminal 19. In one embodiment, the resistive load element 27 is realized by a phase change material sandwiched between the anode terminal 19 and a portion of a top refractory electrode that defines a word line 29 coupled to each thyristor memory cell in a row of the array. Thus, there is a word line 29 for each row of the array (FIG. 3). The word line 29 can be realized from tungsten or other suitable metal. The n-channel injector terminal 23 for each thyristor memory cell in a column of the array is electrically coupled to a bit line (which can be realized from copper or other suitable metal). Thus, there is a bit line for each column of the array (FIG. 3). The p-channel injector terminal 25 for each thyristor memory cell in a column of the array is electrically coupled to an erase line (which can be realized from copper or other suitable metal). Thus, there is an erase line for each column of the array (FIG. 3).

#Preferably, the thyristor memory cell integrated circuit (and possibly other optoelectronic devices, logic circuits and/or signal processing circuits that are fabricated integral thereto) are realized from the inversion quantum-well channel device structures similar to those described in detail in U.S. Pat. No. 6,031,243; U.S. patent application Ser. No. 09/556,285, filed on Apr. 24, 2000; U.S. patent application Ser. No. 09/798,316, filed on Mar. 2, 2001; International Application No. PCT/US02/06802 filed on Mar. 4, 2002; U.S. patent application Ser. No. 08/949,504, filed on Oct. 14, 1997, U.S. patent application Ser. No. 10/200,967, filed on Jul. 23, 2002; U.S. application Ser. No. 09/710,217, filed on Nov. 10, 2000; U.S. Patent Application No. 60/376,238, filed on Apr. 26, 2002; U.S. patent application Ser. No. 10/323,390, filed on Dec. 19, 2002; U.S. patent application Ser. No. 10/280,892, filed on Oct. 25, 2002; U.S. patent application Ser. No. 10/323,390, filed on Dec. 19, 2002; U.S. patent application Ser. No. 10/323,513, filed on Dec. 19, 2002; U.S. patent application Ser. No. 10/323,389, filed on Dec. 19, 2002; U.S. patent application Ser. No. 10/323,388, filed on Dec. 19, 2002; U.S. patent application Ser. No. 10/340,942, filed on Jan. 13, 2003; all of which are hereby incorporated by reference in their entireties. With these structures, a fabrication sequence is used to make all the devices, including an array of thyristor memory cells and supporting electrical and/or optoelectronic devices on a common substrate. In other words, n type and p type contacts, critical etches, etc. are used to realize all of these devices simultaneously on a common substrate. The essential features of this device structure include 1) an n-type modulation doped QW interface 11 and a p-type modulation doped QW interface 13, 2) self-aligned n-type and p-type channel contacts formed by ion implantation, 3) n-type metal for the n-channel injector 23 in contact with the n-type ion implants and the n-type modulation doped QW interface 11 as well as n-type metal for the bottom cathode terminal 21 in contact with the bottom n-type layer 17, 4) p-type metal for the p-type channel injector 25 in contact with the p-type ion implants and the p-type modulation doped QW interface 13 as well as p-type metal for the top anode electrode 19 in contact with the top p-type layer 15; and 5) a current blocking and steering implant in the top p-type region above the n-type modulation doped quantum well interface 11. The n-type modulation doped quantum well interface 11 includes at least one quantum well separated from an n-type doped charge sheet by at least one undoped spacer layer. The p-type modulation doped quantum well interface 13 includes at least one quantum well separated from a p-type doped charge sheet by at least one undoped spacer layer. The active device structures are preferably realized with a material system of group III-V materials (such as a GaAs/AlGaAs).

#In one embodiment, the resistance of the phase change material of the resistive load element 27 of a given thyristor memory cell can be changed between a high resistance phase and a low resistance phase (or vice-versa) in response to electrical current signals that are supplied to the resistive load element 27 via the word line 29 and that flows through the phase change material of the resistive load element 27. The phase change material can be a chalcogenide glass material that is capable of changing phase between a high resistance amorphous phase and a low resistance crystalline phase (and vice versa) by Joule heating of the material through application of current to the material. This operation allows the thyristor memory cell to function in a non-volatile manner. The thyristor memory cell can also function as a volatile static memory cell that does not require periodic refresh, or as a volatile dynamic memory cell that does require periodic refresh as described below.