Memory device
OwnerMasahiro Takahashi, Tsuneo Inaba +2inventors
InventorsMasahiro Takahashi, Tsuneo Inaba, Dong Keun Kim, Ji Wang Lee
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Abstract
According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
Claims20
A memory device comprising:
- a memory cell;
- a sense amplifier comprising a first input and a second input, and configured to output a signal based on a difference between the first and second inputs and be selectively coupled at the second input to the memory cell;
- unit structures each comprising a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series;
- and
- a reference signal generator coupled to the first input of the sense amplifier and comprising:
- a first global line selectively grounded and a second global line selectively grounded;
- a third global line and a fourth global line;
- and
- a first unit structure and a second unit structure of the unit structures, wherein
- the first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line, and
- the second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
A memory device comprising:
- a memory cell;
- a sense amplifier comprising a first input and a second input, and configured to output a signal based on a difference between the first and second inputs and be selectively coupled at the second input to the memory cell;
- unit structures each comprising a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series;
- and
- a reference signal generator coupled to the first input of the sense amplifier and comprising:
- a first global line;
- a second global line selectively grounded;
- and
- a first unit structure and a second unit structure of the unit structures, wherein
- the first unit structure is coupled at the first end to the first global line,
- the second ends of the first and second unit structures are coupled to each other, and
- the second unit structure is coupled at the first end to the second global line.
Dependencies are inferred from the claim text.