Memory cell including unidirectional gate conductors and contacts

A memory cell including a pair of cross-coupled inverters, comprising:

• a first inverter, said first inverter including a substantially rectangular first gate conductor and a first contact;
• a second inverter, said second inverter including a substantially rectangular second gate conductor and a second contact, the second contact substantially aligned with a long axis of the first gate conductor, and the first contact substantially aligned with a long axis of the second gate conductor;
• an access transistor having a gate conductor substantially aligned with a long axis of said first gate conductor;
• a first substantially rectangular active region that intersects at least one of the first gate conductor and the second gate conductor in plan view;
• and
• a second substantially rectangular active region that intersects the gate conductor of the access transistor in plan view;
• wherein, the first active region is non-contiguous with the second active region and has a width in plan view that is greater than a width of the second active region in plan view.

A memory cell including a pair of cross-coupled inverters, comprising:

• a metal 1 layer;
• a first inverter, said first inverter including a substantially rectangular first gate conductor and a first contact;
• a second inverter, said second inverter including a substantially rectangular second gate conductor and a second contact, the second contact substantially aligned with a long axis of the first gate conductor, and the first contact substantially aligned with a long axis of the second gate conductor;
• and
• a buried conductive layer, the buried conductive layer providing connection for a PMOS diffusion, a pull down transistor diffusion, and an access transistor diffusion on each side of the memory cell, and the buried conductive layer lying vertically below and electrically insulated from the metal 1 layer.

A memory cell comprising:

• a plurality of substantially rectangular gate conductors;
• a plurality of substantially rectangular active regions;
• and
• a plurality of metal lines (M1),
• wherein, the plurality of gate conductors are substantially orthogonal to the plurality of active regions,
• the plurality of active regions comprises a first active region and a second active region intersecting at least one of the plurality of gate conductors in plan view, and
• the second active region is non-contiguous with the first active region and has a width in plan view that is larger than a width of the first active region.

A memory cell, comprising:

• a plurality of substantially rectangular active regions including at least a first active region, a second active region, a third active region and a fourth active region;
• a plurality of substantially rectangular gate conductors disposed substantially orthogonal to the plurality of active regions;
• a plurality of metal lines (M1);
• a first inverter including a first pull up transistor and a first pull down transistor;
• a second inverter including a second pull up transistor and a second pull down transistor;
• and
• a first substantially rectangular extended shared contact region having a long axis;
• and
• a second substantially rectangular extended shared contact region having a long axis, wherein:
• the plurality of gate conductors includes a first gate conductor of the first inverter and a second gate conductor of the second inverter;
• the first pull up transistor includes the intersection of the first gate conductor and the first active region;
• the first pull down transistor includes the intersection of the first gate conductor and the second active region;
• the second pull up transistor comprises the intersection of the second gate conductor and the third active region;
• the second pull down transistor comprises the intersection of the second gate conductor and the fourth active region;
• the first active region and the second active region are electrically connected to the first extended shared contact region;
• the third active region and the fourth active region are electrically connected to the second extended shared contact region;
• and
• the long axis of the first extended shared contact region, the long axis of the second extended shared contact region, and the long axis of at least one of the first gate conductor and the second gate conductor are substantially parallel.

A memory cell, comprising:

• a plurality of substantially rectangular active regions including at least a first active region, a second active region, a third active region and a fourth active region;
• a plurality of substantially rectangular gate conductors disposed substantially orthogonal to the plurality of active regions;
• a plurality of metal lines (M1);
• a first inverter including a first pull up transistor and a first pull down transistor;
• a second inverter including a second pull up transistor and a second pull down transistor;
• wherein, the plurality of gate conductors includes a first gate conductor of the first inverter and a second gate conductor of the second inverter,
• the first pull up transistor includes the intersection of the first gate conductor and the first active region,
• the first pull down transistor includes the intersection of the first gate conductor and the second active region,
• the second pull up transistor comprises the intersection of the second gate conductor and the third active region,
• the second pull down transistor comprises the intersection of the second gate conductor and the fourth active region, and
• the plurality of metal lines comprises:
• a first metal line having a long axis;
• and
• a second metal line having a long axis;
• and
• the long axis of the second metal line is substantially aligned with the first gate conductor and the long axis of the first metallic line is substantially aligned with the second gate conductor.

A memory cell, comprising:

• a plurality of substantially rectangular active regions;
• a plurality of substantially rectangular gate conductors disposed substantially orthogonal to the plurality of active regions;
• a plurality of metal lines (M1);
• and
• at least one access transistor, wherein:
• a gate conductor of the at least one access transistor is aligned with a long axis of a first gate conductor in plan view;
• the plurality of active regions includes a first active region intersecting the first gate conductor in plan view;
• the plurality of active regions includes a second active region intersecting the gate conductor of the access transistor in plan view;
• and
• the first active region is non-contiguous with the second active region and has a width in plan view that is larger than a width of the second active region.

A memory cell, comprising:

• a plurality of substantially rectangular active regions;
• a plurality of substantially rectangular gate conductors disposed substantially orthogonal to the plurality of active regions;
• a plurality of metal lines (M1);
• and
• a buried conductive layer, the buried conductive layer providing connection for a PMOS diffusion, a pull down transistor diffusion, and an access transistor diffusion on each side of the memory cell.

A method of forming a memory cell including a pair of cross coupled inverters, said method comprising:

• forming a first substantially rectangular gate conductor;
• forming a gate conductor of a first access transistor;
• forming a first contact;
• forming a second substantially rectangular gate conductor;
• forming a gate conductor of a second access transistor;
• and forming a second contact,
• wherein, at least one of the gate conductor of the first access transistor and the second contact are disposed at a location substantially aligned with a long axis of the first gate conductor, and
• at least one of the gate conductor of the second access transistor and the first contact are disposed at a location substantially aligned with a long axis of the second gate conductor.