Method and circuit for optimizing bit line power consumption

A bit line power optimizing circuit for memory cells having an average and a worst threshold voltages, comprising:

• a bit line discharge oscillator, receiving a supply voltage and converting the supply voltage to a pulse;
• a decoder, coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency;
• a first counter, coupled to the decoder, and receiving the first pulse with the first frequency, and outputting a signal proportional to the average read current;
• a second counter, coupled to the decoder, and receiving the first pulse with the first frequency, and outputting signal proportional to the minimum read current;
• a divider, coupled to the first and the second counters, and outputting a read current ratio of the average read current to the minimum read current;
• a multiplier, coupled to the divider to multiply the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage;
• a power source, providing the supply voltage to the bit line discharge oscillator;
• a first register, coupled to the multiplier, for storing a previous bit line power consumption;
• a comparator, coupled to the multiplier and the first register, receiving a current bit line power consumption, for comparing the current and the previous bit line power consumptions, and outputting a comparison result;
• a second register, for storing the supply voltage;
• and
• an operating unit, coupled to the second register and the comparator, for receiving the comparison result and perform an operation on the supply voltage,
• wherein when the current bit line power consumption is smaller than the previous bit line power consumption, the comparison result makes the operating unit to decreases the supply voltage by a preset amount, and provide the decreased supply voltage to the power source, and
• when the current bit line power consumption is larger than the previous bit line power consumption the comparison result makes the operating unit to deactivate.

A bit line power optimizing method for memory cells, executed by a computing system, the bit line power optimizing method comprising:

• obtaining a word line turn-on time corresponding to a worst bit among the memory cells, wherein a minimum offset voltage is satisfied during the word line turn-on time;
• obtaining an average offset voltage based on the word line turn-on time, wherein the average offset voltage is a function of the supply voltage;
• obtaining a bit line power consumption from the average offset voltage and the supply voltage;
• plotting a diagram of the bit line power consumption versus and the supply voltage according to a condition of the manufacturing process;
• obtaining a target supply voltage at a reverse point where the bit line power consumption versus is minimum;
• and
• outputting the target supply voltage and obtaining an optimized power consumption corresponding to the target supply voltage.