Current source circuits and methods for mass write and testing of programmable impedance elements
AssigneeAdesto Technologies Corporation
InventorsShane Charles Hollmer, John Dinh
Life of this patent
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Abstract
An integrated circuit device can include a plurality of memory cells, each including at least one element programmable between different impedance states by application of a voltage or current; a plurality of bit line groups, each bit line group including multiple bit lines, each bit line being coupled to multiple memory cells; a plurality of current source circuits coupled to the bit line groups, each current source circuit configured to couple the bit lines of its respective group to at least a first bias node or a second bias node.
Claims19
An integrated circuit (IC) device, comprising:
- a plurality of memory cells, each including at least one element programmable between different impedance states by application of a voltage or current;
- a plurality of bit line groups, each bit line group including multiple bit lines, each bit line being coupled to multiple memory cells;
- a plurality of current source circuits coupled to the bit line groups, each current source circuit configured to couple the bit lines of its respective group to at least a first bias node or a second bias node;
- a controller circuit configured to generate current source control signals in response to input mode data;
- and
- the two current source circuits are configured to couple corresponding bit line groups to at least the first or second bias nodes in response to the current control signals.
A method, comprising
- coupling a first bit line group to one of a plurality of different bias nodes in response to a first control signal;
- coupling a second bit line group to one of the different bias nodes in response to a second control signal;
- and
- the first and second bit lines groups each include a plurality of bit lines, each bit line is coupled to a column of memory cells, and each memory cell includes at least one element programmable between at least two different impedance states;
- wherein,
- the bias nodes include a first bias node configured to receive a first potential;
- and
- coupling the first bit line group to the first bias node writes a first data value into memory cells coupled to the first bit line group.
An integrated circuit (IC) device, comprising:
- at least one memory cell array including memory cells arranged into rows and columns, memory cells of the same column being coupled to a same bit line, and each memory cell including at least one element programmable between different impedance states;
- current source circuits disposed on one side of the memory cell array, each current source circuit configured to independently connect a different group of bit lines to one of a plurality of different bias nodes;
- and
- column sensing circuits disposed on a side of the memory cell array opposite to the current source circuits, the column sensing circuits configured to sense currents flowing through the bit lines.
Dependencies are inferred from the claim text.