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US 8,947,903 B2Granted
Memory chip with more than one type of memory cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng Hung Lee, XiuLi Yang, Liangbo Zhuang
Life of this patent
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Abstract
A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.
Claims20
A semiconductor chip comprising:
- a plurality of word lines configured to be driven by respective word line drivers;
- a plurality of bit lines configured to transmit signals to respective bit line amplifiers/drivers;
- and
- a plurality of memory cells, at least one memory cell of the plurality of memory cells at an intersection of a respective word line and a respective bit line, the at least one memory cell of a type selected from a plurality of memory cell types based on a distance of the intersection from an end of at least one of the respective bit line or the respective word line.
1 more element
A semiconductor chip comprising:
- a plurality of word lines configured to be driven by respective word line drivers;
- a plurality of bit lines configured to transmit signals to respective bit line amplifiers/drivers;
- and
- a plurality of memory cells, at least one memory cell of the plurality of memory cells at an intersection of a respective word line and a respective bit line, the at least one memory cell of a type selected from a first memory cell type or a second memory cell type based on a distance of the intersection from an end of at least one of the respective bit line or the respective word line,
- wherein the second memory cell type has a larger cell area than the first area memory cell type, and the first memory cell type has a same length in a direction of the word lines as the second memory cell type.
2 more elements
A semiconductor chip comprising:
- a plurality of word lines configured to be driven by respective word line drivers;
- a plurality of bit lines configured to transmit signals to respective bit line amplifiers/drivers;
- and
- a plurality of memory cells, at least one memory cell of the plurality of memory cells at an intersection of a respective word line and a respective bit line, the at least one memory cell of a type selected from a plurality of memory cell types based on a distance of the intersection from an end of at least one of the respective bit line or the respective word line,
- wherein the memory cell types selected for the at least one memory cell at the intersection are based on a number of intersections between the intersection and the respective bit line amplifier, and an area of the memory cell types selected increases as the number of intersections increases.
2 more elements
Dependencies are inferred from the claim text.