Content addressable memory chip
AssigneeRenesas Electronics Corporation
InventorMasanobu Kishida
Life of this patent
Estimating the term…
Abstract
A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of a match line. The match amplifier zone comprises one or more NMOS transistors and one or more PMOS transistors. The match amplifier zone has a dead zone to an input of a voltage of the match line, and has a property that no flow-through current is present in the match amplifier zone.
Claims16
A content addressable memory chip, comprising:
- a plurality of entries each having a plurality of content addressable memory cells in a memory array;
- a plurality of match lines, arranged corresponding to the respective entries, each coupled to the plurality of content addressable memory cells in a corresponding one of the entries;
- and
- a plurality of match amplifiers, each coupled to an associated one of the match lines and a match amplifier enable signal line, and detecting a voltage on the associated one of the match lines,
- wherein each of match amplifiers comprises a NAND circuit receiving the voltage on the associated one of the match lines and a voltage on the match amplifier enable signal line,
- wherein the NAND circuit comprises a first NMOS transistor having a gate coupled to the associated one of the match lines, a source coupled to a ground and a drain, and having a first threshold value higher than a threshold value of a standard NMOS transistor composing the content addressable memory cells.
A content addressable memory chip, comprising:
- a plurality of entries each having a plurality of content addressable memory cells in a memory array;
- a plurality of match lines, arranged corresponding to the respective entries, each coupled to the of plurality content addressable memory cells in a corresponding one of the entries;
- and
- a plurality of match amplifiers, each detecting a voltage on the associated one of the match lines,
- wherein the memory array and the match lines are divided into a first to 2n-th block (n is a natural number),
- wherein each of the match amplifiers comprises:
- a first to a n-th determination circuit coupled in series such that the output of a preceding one of the determination circuit is supplied to a succeeding one of the determination circuits, and
- a latch that latches and outputs an output of the n-th determination circuit,
- wherein the i-th determination circuit (1≦i≦n) comprises:
- a first and a second NAND circuit arranged between the (2i−1)-th block and the 2i-th block, and coupling a match line of the (2i−1)-th block and a match line of the 2i-th block, respectively, and
- a logic circuit that performs a logical operation of an output of the first and the second NAND circuit and an output of the preceding determination circuit, and outputs the logical operation result as the output of the determination circuit, and
- wherein the first NAND circuit comprises a first NMOS transistor having a gate coupled to the match line of the (2i−1)-th block, a source coupled to a ground and a drain,
- wherein the second NAND circuit comprises a second NMOS transistor having a gate coupled to the match line of the 2i-th block, a source coupled to a ground and a drain, and
- wherein the first and the second NMOS transistor comprises a first threshold value higher than a threshold value of a standard NMOS transistor composing the content addressable memory cells.
Dependencies are inferred from the claim text.