Stable SRAM cell

A static random access memory (SRAM) cell comprising:

• a latch means for latching a first value on a first storage node and a second value on a second storage node;
• an enabling means for enabling access to the latch means;
• and
• a first pass means for coupling a first bit line to the first storage node, the first pass means being responsive to the enabling means when both a word line and a column select line are asserted.

A memory cell array having a plurality of memory cells arranged in a plurality of rows and columns, the memory cell array comprising:

• a plurality of bit line pairs and a plurality of column-select lines for accessing a column of the plurality of columns of the memory cell array;
• and
• a plurality of word lines for accessing a row of the plurality of rows of the memory cell array, wherein each memory cell in the memory cell array comprising:
• a latch circuit, wherein outputs of the latch circuit are a first storage node and a second storage node;
• a switch enabled by a first column-select line of the plurality of column-select lines;
• and
• a first pass-gate coupling a first bit line of the plurality of bit line pairs and the first storage node, wherein the first pass-gate is enabled by the switch.