Active matrix substrate and display device

An active matrix substrate comprising:

• a substrate;
• a gate bus line provided on the substrate;
• a source bus line provided on the substrate so as to intersect the gate bus line;
• a TFT provided near an intersection between the gate bus line and the source bus line, the TFT having a gate electrode electrically connected to the gate bus line, a source electrode electrically connected to the source bus line, and a drain electrode;
• a pixel electrode electrically connected to the drain electrode of the TFT;
• a storage capacitor bus line provided in parallel to the gate bus line or the source bus line;
• a storage capacitor counter electrode electrically connected to the drain electrode to create a storage capacitance with the storage capacitor bus line, wherein
• the storage capacitor counter electrode includes:
• a first portion overlapping the storage capacitor bus line to create a substantial storage capacitance;
• a second portion interposed between the first portion and the drain electrode;
• and
• a third portion being provided opposite from the second portion with the first portion sandwiched therebetween, the third portion protruding from the first portion and overlapping the storage capacitor bus line, but not overlapping any pixel electrode other than the pixel electrode electrically connected to the drain electrode of the TFT;
• a plurality of pixels are defined;
• and
• in at least two pixels among the plurality of pixels, a position of the third portion within the pixel differs.

A display device comprising:

• an active matrix substrate including:
• a substrate;
• a gate bus line provided on the substrate;
• a source bus line provided on the substrate so as to intersect the gate bus line;
• a TFT provided near an intersection between the gate bus line and the source bus line, the TFT having a gate electrode electrically connected to the gate bus line, a source electrode electrically connected to the source bus line, and a drain electrode;
• a pixel electrode electrically connected to the drain electrode of the TFT;
• a storage capacitor bus line provided in parallel to the gate bus line or the source bus line;
• and
• a storage capacitor counter electrode electrically connected to the drain electrode to create a storage capacitance with the storage capacitor bus line, wherein
• the storage capacitor counter electrode includes:
• a first portion overlapping the storage capacitor bus line to create a substantial storage capacitance;
• a second portion interposed between the first portion and the drain electrode;
• and
• a third portion being provided opposite from the second portion with the first portion sandwiched therebetween, the third portion protruding from the first portion and overlapping the storage capacitor bus line, but not overlapping any pixel electrode other than the pixel electrode electrically connected to the drain electrode of the TFT;
• a counter substrate disposed opposite from the active matrix substrate;
• and
• a display medium layer disposed between the active matrix substrate and the counter substrate wherein
• the display medium layer is a liquid crystal layer;
• at least one of the active matrix substrate and the counter substrate has a black matrix;
• and
• the third portion of the storage capacitor counter electrode is disposed at a position overlapping the black matrix.