Display device

A display device having a pixel circuit array comprising a plurality of pixel circuits arranged in a row direction and a column direction, respectively, wherein

• each of the pixel circuits has:
• a display element part including a unit display element;
• an internal node composing a part of the display element part, for holding a pixel data voltage applied to the display element part;
• a first switch circuit;
• a second switch circuit;
• and a control circuit including a first capacitive element,
• the second switch circuit has one end connected to the internal node and has a series circuit of a first transistor element and a diode element,
• the control circuit has a series circuit of the first capacitive element and a second transistor element, a first terminal of the second transistor element is connected to the internal node, and a second terminal of the second transistor element is connected to a control terminal of the first transistor and one end of the first capacitive element to form an output node,
• the first switch circuit has one end connected to the internal node, and includes a third transistor element,
• a common electrode is connected to a terminal opposite to a terminal connected to the internal node, among terminals of the unit display element,
• the other end of the first switch circuit and the other end of the second switch circuit in each of the pixel circuits arranged in the same column are connected to one of data signal lines in common,
• a control terminal of the third transistor element in each of the pixel circuits arranged in the same row is connected to one of scan signal lines in common,
• a control terminal of the second transistor element in each of the pixel circuits arranged in the same row or the same column is connected to one of first control lines in common,
• the other end of the first capacitive element in each of the pixel circuits arranged in the same row or the same column is connected to one of second control lines in common,
• a data signal line drive circuit for driving the data signal lines individually, a control line drive circuit for driving the first and second control lines individually, and a scan line drive circuit for driving the scan signal lines individually are provided,
• the internal node of each of the pixel circuits in the pixel circuit array holds one voltage state among a plurality of discrete voltage states, in which multi-gradation is implemented by the different voltage states,
• at a time of a self-refreshing action for compensating voltage fluctuations of the internal nodes at the same time by activating the second switch circuits and the control circuits in the plurality of the pixel circuits while sequentially changing a target gradation to be subjected to the self-refreshing action,
• the scan signal line drive circuit applies a predetermined voltage to the scan signal lines connected to all of the pixel circuits in the pixel circuit array to turn off the third transistor elements,
• the data signal line drive circuit applies a refreshing input voltage to the data signal lines, the refreshing input voltage being provided by adding a predetermined first adjusting voltage corresponding to a voltage drop in the second switch circuit, to a refreshing desired voltage corresponding to the voltage state of the target gradation to be subjected to a refreshing action,
• the control line drive circuit applies a refreshing reference voltage to the first control lines, the refreshing reference voltage being provided by adding a predetermined second adjusting voltage corresponding to a voltage drop in the first control lines and the internal node, to a refreshing isolation voltage defined by a middle voltage between a voltage state of a gradation one step lower than the target gradation and the voltage state of the target gradation, and applies a boost voltage having a predetermined amplitude to the second control lines so as to apply a voltage change due to capacitive coupling through the first capacitive element to the output node, so that, when the voltage state of the internal node is higher than the refreshing desired voltage, the diode element is reversely biased from each of the data signal lines to the internal node, and each of the data signal lines and the internal node are not connected, when the voltage state of the internal node is lower than the refreshing isolation voltage, a potential fluctuation of the output node due to application of the boost voltage is suppressed, the first transistor element is turned off, and each of the data signal lines and the internal node are not connected, and when the voltage state of the internal node is not less than the refreshing isolation voltage and not more than the refreshing desired voltage, the diode element is forwardly biased from each of the data signal lines to the internal node, the potential fluctuation of the output node is not suppressed, the first transistor element is turned on, and the refreshing desired voltage is applied to the internal node, so that the refreshing action is executed for the pixel circuit having the internal node showing the voltage state of the target gradation,
• with the boost voltage continuously applied, the target gradation is set to a one step higher gradation, the refreshing reference voltage applied to the first control lines is changed, and thereafter the refreshing input voltage applied to the data signal lines is changed, so that the refreshing action is sequentially executed for the pixel circuits having the internal nodes showing voltage states of different gradations, and
• after the refreshing action is performed for all of the gradations except for a lowest gradation, the control line drive circuit reduces a voltage applied to the first control lines to turn off the second transistor elements in all of the gradations, the application of the boost voltage to the second control lines is stopped, and then the voltage applied to the first control lines is increased to turn on the second transistor elements in all of the gradations.