Display driving system using transmission of single-level embedded with clock signal

A display driving system comprising:

• a timing control section comprising:
• an LVDS receiving unit configured to receive and output data signals;
• a data processing unit configured to temporarily store the data signals outputted from the LVDS receiving unit and output the data signals to a transmission unit;
• a timing generation unit configured to generate clock signals and timing control signals;
• and
• the transmission unit configured to:
• receive the data signals outputted from the data processing unit and the clock signals outputted from the timing generation unit;
• generate first clock signals comprising clock signals but not data signals;
• generate second clock signals in which clock signals are embedded between data signals;
• transmit, at a first time, the first clock signals to a panel driving section;
• and
• transmit, at a second time, the second clock signals embedded between data signals to the panel driving section;
• and
• the panel driving section comprising:
• row driving units configured to sequentially emit gate signals toward a display panel;
• and
• column driving units configured to receive the first clock signals transmitted through signal lines from the transmission unit, receive the second clock signals embedded between data signals transmitted through the signal lines from the transmission unit, and supply the received signals to the display panel,
• wherein, in the second clock signals embedded between the data signals, the data signals and the clock signals embedded between the data signals are single and same level signals such that the amplitudes of the data signals and the clock signals embedded between the data signals are the same as they are transmitted,
• wherein, the first clock signals are transmitted from the transmission unit in series through the column driving units before and during transmission of the second clock signals and the data signals to the column driving units to start clock training, and the second clock signals embedded between the data signals and the data signals are transmitted through the same signal line.