Driving circuit and display device using multiple phase clock signals
AssigneeJapan Display Inc.
InventorsMotoharu Miyamoto, Takahiro Ochiai
Life of this patent
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Abstract
In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.
Claims6
A driving circuit of a display device, the driving circuit being configured to output an active potential sequentially to a plurality of scanning signal lines, the active potential setting a transistor conductive, the driving circuit comprising:
- a plurality of output circuits electrically connected respectively to the plurality of scanning signal lines, wherein one output circuit of the plurality of output circuits includes:
- a first transistor which controls electrical connection between one scanning signal line of the plurality of scanning signal lines and a clock signal line,
- a first node which is connected to a gate of the first transistor and is at the active potential in a first time period including a time period during which the active potential is output to the scanning signal line,
- a second transistor which controls to connect the first node and an inactive signal line electrically in a second time period other than the first time period,
- wherein the inactive signal retains an inactive potential which does not set the transistor conductive, and
- a second node which is connected to a gate of the second transistor, wherein the second node is charged at first and second charging times for retaining the active potential,
- wherein the clock signal line is configured to supply a first clock signal, further comprising:
- a first charging line which is connected to the second node and which is configured to supply a second clock signal,
- a second charging line which is connected to the second node and which is configured to supply a third clock signal,
- wherein each of the first, second and third clock signals is one of 8-phase clock signals and wherein all of the first, second and third clock signals have a same period and a different phase from each other,
- wherein the second clock signal charges the second node at the first charging time, and
- wherein the third clock signal charges the second node at the second charging time.
Dependencies are inferred from the claim text.