Pixel circuit, method of driving a pixel circuit, and organic light emitting display device
AssigneeSamsung Display Co., Ltd.
InventorYoung-In Hwang
Life of this patent
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Abstract
A pixel circuit includes an organic light emitting diode, a first PMOS transistor coupled between a first power voltage and an anode electrode of the organic light emitting diode, a second PMOS transistor coupled between a first node and the anode electrode of the organic light emitting diode, a first capacitor coupled between a second node and the first node, a second capacitor coupled between the first power voltage and the second node, a third PMOS transistor coupled between a data line and the second node, a fourth PMOS transistor coupled between a third node and the second node, a third capacitor coupled between the third node and a gate terminal of the third PMOS transistor, and a fifth PMOS transistor coupled between the data line and the third node.
Claims16
A pixel circuit, comprising:
- an organic light emitting diode, a cathode electrode of the organic light emitting diode being coupled to a second power voltage;
- a first PMOS transistor coupled between a first power voltage and an anode electrode of the organic light emitting diode, a gate terminal of the first PMOS transistor being coupled to a first node;
- a second PMOS transistor coupled between the first node and the anode electrode of the organic light emitting diode, a gate terminal of the second PMOS transistor receiving a compensation control signal;
- a first capacitor coupled between a second node and the first node;
- a second capacitor coupled between the first power voltage and the second node;
- a third PMOS transistor coupled between a data line and the second node, a gate terminal of the third PMOS transistor receiving the compensation control signal;
- a fourth PMOS transistor coupled between a third node and the second node, a gate terminal of the fourth PMOS transistor receiving an emission control signal;
- a third capacitor coupled between the third node and the gate terminal of the third PMOS transistor;
- and
- a fifth PMOS transistor coupled between the data line and the third node, a gate terminal of the fifth PMOS transistor being coupled to a scan line.
Dependencies are inferred from the claim text.