Pipeline A/D converter and A/D converting method

A pipeline A/D converter configured to convert an analog input voltage into digital data, the pipeline A/D converter comprising an A-type converter circuit, at least one B-type converter circuit, and a comparator array, connected in series,

• wherein the A-type converter circuit comprises:
• a first sub-A/D converter configured to compare the input voltage with a plurality of threshold voltages, and to judge which one from among a plurality of segments the input voltage belongs to;
• a first amplifier circuit configured to generate a first voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the input voltage belongs, to generate a third voltage by amplifying the difference between the first voltage and the input voltage with a predetermined common voltage as a base, and to output the third voltage to the B-type converter circuit arranged as a downstream stage;
• and
• a second amplifier circuit configured to generate a second voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the input voltage belongs, to generate a fourth voltage by amplifying the difference between the second voltage and the input voltage with the common voltage as a base, and to output the fourth voltage to the B-type converter circuit arranged as a downstream stage,
• and wherein the B-type converter circuit comprises:
• a second-sub A/D converter configured to divide a range between the third voltage and the fourth voltage received from the upstream stage into a plurality of segments, and to judge which one from among the plurality of segments the common voltage belongs to;
• a third amplifier circuit configured to generate a seventh voltage by amplifying the difference between the common voltage and a fifth voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the common voltage belongs, and to output the seventh voltage as the third voltage to the B-type converter circuit arranged as the downstream stage;
• and
• a fourth amplifier circuit configured to generate an eighth voltage by amplifying the difference between the common voltage and a sixth voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the common voltage belongs, and to output the eighth voltage as the fourth voltage to the B-type converter circuit arranged as the downstream stage,
• and wherein the comparator array is configured to divide a range between the third voltage and the fourth voltage received from the B-type converter circuit arranged as the immediately upstream stage into a plurality of segments, and to judge which one from among a plurality of segments the common voltage belongs to.

A dynamic differential amplifier comprising:

• a first input terminal and a second input terminal;
• a first output terminal and a second output terminal;
• a first load capacitor arranged between the first output terminal and a fixed voltage terminal;
• a second load capacitor arranged between the second output terminal and the fixed voltage terminal;
• an initializing circuit configured to initialize the charge stored in each of the first load capacitor and the second load capacitor;
• an input differential pair comprising a first input transistor and a second input transistor arranged such that the first load capacitor and the second load capacitor respectively function as their load, and their control terminals are respectively connected to the first input terminal and the second input terminal;
• and
• a control circuit configured to disconnect a charging/discharging path for the first load capacitor and the second load capacitor when the midpoint voltage of the electric potentials at the first output terminal and the second output terminal reaches a predetermined threshold voltage.