Method and apparatus for calibrating digital background through capacitor division and swapping for reducing capacitor mismatch effect of analog-to-digital converter
AssigneePostech Academy-Industry Foundation
InventorsJae Yoon Sim, Hwa Suk Cho
Life of this patent
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Abstract
A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR).
Claims13
A digital background calibration apparatus using capacitor division and swapping in order to reduce a capacitor mismatch effect of an Analog to Digital Converter (ADC), the apparatus comprising:
- a Digital to Analog Converter (DAC) configured to select any one of an input signal, a ground voltage, and a reference voltage in response to a first control signal and a second control signal, convert the selected signal or voltage into an analog signal, and output a first conversion signal and a second conversion signal as the converted analog signal;
- a comparator configured to convert the first conversion signal and the second conversion signal into digital signals, output a first digital signal and a second digital signal as the converted digital signals, and output a third digital signal as a comparison value of the first conversion signal and the second conversion signal;
- a Successive Approximation Register (SAR) configured to output a first register signal and a second register signal using the first digital signal and the second digital signal and output the first control signal using the third digital signal;
- a calibration unit configured to output a digital code calibration signal by calibrating a mismatch value of the first register signal in response to an external control signal;
- and
- a bit controller configured to output the second control signal using the second register signal in response to the external control signal,
- wherein the digital code calibration signal is fed back to one side of the calibration unit, and the input signal comprises a first input signal and a second input signal.
A digital background calibration method through capacitor division and swapping in order to reduce a capacitor mismatch effect of an ADC, the method comprising:
- using a digital to analog convertor to perform a conversion step comprising selecting one of an input signal, a ground voltage, and a reference voltage in response to a first control signal and a second control signal and outputting a plurality of analog signals as a selected signal;
- using a comparator to perform a comparison step comprising outputting a first digital signal and a second digital signal converted from the plurality of analog signals, comparing the plurality of analog signals with each other, and outputting a third digital signal as a result of the comparison;
- using a successive approximation register to perform a register step comprising outputting a first register signal and a second register signal by dispersing the first digital signal and the second digital signal into the first register signal and the second register signal and outputting the third digital signal as a first control signal in the conversion step;
- using a calibration unit to perform a calibration step comprising outputting a calibrated value by calibrating a mismatch value of the first register signal in response to an external control signal and feeding back the calibrated and output value;
- and
- using a bit controller to perform a control step of comprising outputting the second register signal as the second control signal using the external control signal.
Dependencies are inferred from the claim text.