Apparatus and method to accelerate compression and decompression operations
AssigneeIntel Corporation
InventorsVinodh Gopal, James D. Guilford, Gilbert M. Wolrich
Life of this patent
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Abstract
A processor is described that includes an instruction execution pipeline having an instruction fetch unit to fetch and decode an instruction. The processor also has an execution unit to execute the instruction. The execution unit has a state machine and content addressable memory (CAM) circuitry. The state machine is to receive a pointer to a stream of DEFLATE encoded information, fetch a section of the DEFLATE encoded information and apply the section of the DEFLATE encoded information to the CAM to obtain decoded DEFLATE information.
Claims21
A processor, comprising:
- an instruction execution pipeline having:
- an instruction fetch unit to fetch and decode an instruction;
- and
- an execution unit to execute the instruction, the execution unit comprising a state machine and content addressable memory (CAM) circuitry, the state machine to receive a pointer to a stream of DEFLATE encoded information, fetch a section of the DEFLATE encoded information, and apply the section of the DEFLATE encoded information to the CAM to obtain decoded DEFLATE information.
A method, comprising:
- fetching an instruction;
- decoding the instruction;
- executing the instruction on a processor, where the executing of the instruction includes:
- receiving a pointer to a stream of DEFLATE encoded information;
- fetching a section of the DEFLATE encoded information;
- and
- applying the section of the DEFLATE encoded information to a content addressable memory (CAM) to obtain a decoded DEFLATE information.
A non-transitory machine readable storage medium having instructions that when processed by a computing system cause a method to be performed, said method comprising:
- constructing software code by:
- introducing a first instruction that accepts a pointer to DEFLATE encoded information and decodes a section of said DEFLATE encoded information to produce a decoded section of DEFLATE information and an updated pointer that accounts for said decoded section's size;
- and
- introducing a loop operation to re-execute said instruction using said updated pointer as an input operand.
A non-transitory machine readable storage medium having instructions that when processed by a computing system cause a method to be performed, said method comprising:
- executing a first instruction that accepts a pointer to DEFLATE encoded information and decodes a section of said DEFLATE encoded information to produce a decoded section of DEFLATE information and an updated pointer that accounts for said decoded section's size;
- and
- executing a loop operation to re-execute a second instruction of same type as said instruction that uses as an input operand a respective updated pointer from a previous instruction of said same type.
Dependencies are inferred from the claim text.