Stacked clock distribution for low power devices

A clock distribution device, the clock distribution device comprising:

• a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals, wherein the stacked clock driver circuit comprises:
• a first-half driver circuit configured to receive a first input clock signal that swings between a voltage threshold and one half of the voltage threshold and to generate a first output clock signal that swings between the voltage threshold and one half of the voltage threshold;
• and
• a second-half driver circuit connected to the first-half driver circuit and configured to receive a second input clock signal that swings between one half of the voltage threshold and zero and generate a second output clock signal that swings between one half of the voltage threshold and zero;
• and
• a load circuit comprising a PMOS load network having only PMOS transistors and an NMOS load network having only NMOS transistors, wherein the PMOS load network is configured to be driven by the first output clock signal, and wherein the NMOS load network is configured to be driven by the second output clock signal.