Apparatus for high rotation rate low I/O count phase interpolator
AssigneeBroadcom Corporation
InventorWei Zhang
Life of this patent
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Abstract
Methods and apparatuses for high rotation rate low I/O count phase interpolation are disclosed, including techniques to reduce redundant phase interpolation coding and method steps by modifying phase mapping and generation with pluralities of amplifiers. I/O reduction count is achieved while maintaining resolution and allowing scalability in phase interpolation. Control circuits include techniques to interpolate phases at a high rotation rate while reducing discontinuities and risk for logic hazards.
Claims20
A phase interpolator, comprising:
- an in-phase amplifier configured to amplify an in-phase signal, including
- a plurality of first type amplifiers responsive to a plurality of corresponding control signals, each of the plurality of first type amplifiers configured to amplify the in-phase signal by a unit gain amount when activated by the corresponding control signal;
- a second type amplifier, coupled in parallel with the plurality of first type amplifiers, and configured to amplify the in-phase signal by one-half of the unit gain;
- and
- a summing node that sums outputs of the plurality of first type amplifiers and an output of the second type amplifier,
- wherein each of the plurality of first type amplifiers are switchably connected to an output of the in-phase amplifier responsive to the corresponding control signals so that a gain of the in-phase amplifier can be tuned in increments of the unit gain amount, and
- wherein the second type amplifier is connected to the summing node in a non-switchable manner so that the gain of the in-phase amplifier includes at least the one-half of the unit gain.
An apparatus to interpolate a phase of a signal, the signal comprising a first component and a second component, the apparatus comprising:
- a first switch, configured to couple at least one of the first component and an anti-phase of the first component to an output of the first switch, in response to a first switch control signal;
- a second switch, configured to couple at least one of the second component and an anti-phase of the second component, to an output of the second switch, in response to a second switch control signal;
- a first amplifier, coupled to the first switch output and a summing node, configured to amplify the output of the first switch by a first quantity;
- a second amplifier, coupled to the second switch output and the summing node, configured to amplify the output of the second switch by the first quantity;
- a first plurality of amplifiers, coupled in parallel between the first switch and the summing node, each of the first plurality of amplifiers configured to selectively amplify the output of the first switch by a second quantity, in response to at least one of a first plurality of amplifier control signals;
- and
- a second plurality of amplifiers, coupled in parallel between the second switch and the summing node, each of the second plurality of amplifiers configured to selectively amplify the output of the second switch by the second quantity, in response to at least one of a second plurality of amplifier control signals.
Dependencies are inferred from the claim text.